Computer organisation

Computer organisation

• 1.
  Computer Organization Computerdesign as an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine Inputs = machine instruction, datapath conditions Outputs = register transfer control signals, ALU operation codes Instruction interpretation = instruction fetch, decode, execute Datapath = functional units + registers Functional units = ALU, multipliers, dividers, etc. CS 150 - Fakk 2000 - Computer Registers = program counter, shifters, storage registers Organization - 1
• 2.
  Structure of aComputer Block diagram view address Processor read/write Memory System central processing data unit (CPU) control signals Control Data Path data conditions instruction unit execution unit – instruction fetch and – functional units interpretation FSM CS 150 - Fakk 2000 - Computer and registers Organization - 2
• 3.
  Registers Selectively loaded– EN or LD input Output enable – OE input Multiple registers – group 4 or 8 in parallel LD OE D7 Q7 OE asserted causes FF state to be D6 Q6 connected to output pins; otherwise they D5 Q5 are left unconnected (high impedance) D4 Q4 D3 Q3 D2 Q2 LD asserted during a lo-to-hi clock D1 Q1 transition loads new data into FFs D0 CLK Q0 CS 150 - Fakk 2000 - Computer Organization - 3
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  Register Transfer Point-to-pointconnection MUX MUX MUX MUX Dedicated wires Muxes on inputs of rs rt rd R4 each register Common input from multiplexer Load enables for each register rs rt rd R4 Control signals MUX for multiplexer Common bus with output enables Output enables and load rs rt rd R4 enables for each register CS 150 - Fakk 2000 - ComputerBUS Organization - 4
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  Register Files Collections of registers in one package Two-dimensional array of FFs Address used as index to a particular word Separate read and write addresses so can do both at same time 4 by 4 register file 16 D-FFs Organized as four words of four bits each RE Write-enable (load) RB RA Read-enable (output enable) WE Q3 WB Q2 WA Q1 Q0 D3 D2 D1 CS 150 - Fakk 2000 - Computer D0 Organization - 5
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  Memories LargerCollections of Storage Elements Implemented not as FFs but as much more efficient latches High-density memories use 1-5 switches (transitors) per bit Static RAM – 1024 words each 4 bits wide Once written, memory holds forever (not true for denser dynamic RAM) Address lines to select word (10 lines for 1024 words) Read enable RD Same as output enable WR Often called chip select A9 Permits connection of many A8 IO3 A7 IO2 chips into larger array A6 IO1 A5 Write enable (same as load enable) A4 IO0 Bi-directional data lines A3 A2 outputCS 150 - Fakk 2000 - Computer when reading, input when writing A2 A1 A0 Organization - 6
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  Instruction Sequencing Example– an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz) Step 1: Get the ADD instruction from memory into an instruction register Step 2: Decode instruction Instruction in IR has the code of an ADD instruction Register indices used to generate output enables for registers Rx and Ry Register index used to generate load signal for register Rz Step 3: execute instruction Enable Rx and Ry output and direct to ALU Setup ALU to perform ADD operation CS 150 - Fakk 2000 - Computer Direct result to Rz so that it can be loaded into register Organization - 7
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  Instruction Types DataManipulation Add, subtract Increment, decrement Multiply Shift, rotate Immediate operands Data Staging Load/store data to/from memory Register-to-register move Control Conditional/unconditional branches in program flow Subroutine call and return CS 150 - Fakk 2000 - Computer Organization - 8
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  Elements of theControl Unit (aka Instruction Unit) Standard FSM Elements State register Next-state logic Output logic (datapath/control signalling) Moore or synchronous Mealy machine to avoid loops unbroken by FF Plus Additional ”Control" Registers Instruction register (IR) Program counter (PC) Inputs/Outputs Outputs control elements of data path Inputs from data path used to alter flow of program (test if zero) CS 150 - Fakk 2000 - Computer Organization - 9
• 10.
  Instruction Execution Control State Diagram (for each diagram) Reset Reset Fetch instruction Init Initialize Decode Machine Execute Fetch Instructions partitioned Instr. into three classes Branch Load/ XEQ Load/store Branch Store Instr. Register- Register-to-register to-Register Branch Branch Different sequence Taken Not Taken Incr. through diagram for PC each instruction type 2000 - Computer CS 150 - Fakk Organization - 10
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  Data Path (Hierarchy) Arithmetic circuits constructed in hierarchical and Cin iterative fashion each bit in datapath is Ain functionally identical FA Sum Bin 4-bit, 8-bit, 16-bit, 32-bit datapaths Cout Ain Sum HA Bin Cout HA Cin CS 150 - Fakk 2000 - Computer Organization - 11
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  Data Path (ALU) ALU Block Diagram Input: data and operation to perform Output: result of operation and status information A B 16 16 Operation 16 N S Z CS 150 - Fakk 2000 - Computer Organization - 12
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  Data Path (ALU+ Registers) Accumulator Special register One of the inputs to ALU Output of ALU stored back in accumulator One-address instructions Operation and address of one operand 16 Other operand and destination is accumulator register REG AC 16 16 AC <– AC op Mem[addr] ”Single address instructions” OP (AC implicit operand) N Multiple registers 16 Z Part of instruction used CS 150 - Fakk 2000 - Computer to choose register operands Organization - 13
• 14.
  Data Path (Bit-slice) Bit-slice concept: iterate to build n-bit wide datapaths CO ALU CI CO ALU ALU CI AC AC AC R0 R0 R0 rs rs rs rt rt rt rd rd rd from from from memory memory memory CS 150 - Fakk 2000 - Computer wide 1 bit wide 2 bits Organization - 14
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  Instruction Path Program Counter Keeps track of program execution Address of next instruction to read from memory May have auto-increment feature or use ALU Instruction Register Current instruction Includes ALU operation and address of operand Also holds target of jump instruction Immediate operands Relationship to Data Path PC may be incremented through ALU Contents of IR may also be required as input to ALU CS 150 - Fakk 2000 - Computer Organization - 15
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  Data Path (MemoryInterface) Memory Separate data and instruction memory (Harvard architecture) Two address busses, two data busses Single combined memory (Princeton architecture) Single address bus, single data bus Separate memory ALU output goes to data memory input Register input from data memory output Data memory address from instruction register Instruction register from instruction memory output Instruction memory address from program counter Single memory Address from PC or IR Memory output to-instruction and data registers CS 150 Fakk 2000 - Computer Memory input from ALU- output Organization 16
• 17.
  Block Diagram ofProcessor Register Transfer View of Princeton Architecture Which register outputs are connected to which register inputs Arrows represent data-flow, other are control signals from control FSM load 16 path MAR may be a simple multiplexer rather than separate register REG AC rd wr 16 16 store data path MBR is split in two OP Data Memory (16-bit words) (REG and IR) N addr 8 Load control Z for each register Control FSM MAR 16 IR PC 16 16 OP CS 150 - Fakk 2000 - Computer 16 Organization - 17
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  Block Diagram ofProcessor Register transfer view of Harvard architecture Which register outputs are connected to which register inputs Arrows represent data-flow, other are control signals from control FSM 16 load path Two MARs (PC and IR) REG AC rd wr Two MBRs (REG and IR) 16 16 store data path Data Memory Load control for each register OP (16-bit words) N addr 16 Z Control 16 FSM IR PC data 16 16 Inst Memory (8-bit words) OP addr CS 150 - Fakk 2000 - Computer 16 Organization - 18
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  A simplified ProcessorData-path and Memory Princeton architecture memory has only 255 words with a display on the last one Register file Instruction register PC incremented through ALU Modeled after MIPS rt000 (used in 378 textbook by Patterson & Hennessy) Really a 32 bit machine CS 150 - Fakk 2000 - Computer We’ll do a 16 bit version Organization - 19
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  Processor Control Synchronous Mealy machine Multiple cycles per instruction CS 150 - Fakk 2000 - Computer Organization - 20
• 21.
  Processor Instructions Threeprincipal types (16 bits in each instruction) type op rs rt rd funct R(egister) 3 3 3 3 4 I(mmediate) 3 3 3 7 J(ump) 3 13 Some of the instructions add 0 rs rt rd 0 rd = rs + rt R sub 0 rs rt rd 1 rd = rs - rt and 0 rs rt rd 2 rd = rs & rt or 0 rs rt rd 3 rd = rs | rt slt 0 rs rt rd 4 rd = (rs < rt) lw 1 rs rt offset rt = mem[rs + offset] I sw 2 rs rt offset mem[rs + offset] = rt beq 3 rs rt offset pc = pc + offset, if (rs == rt) addi 4 rs rt offset rt = rs + offset J j 5 target address pc = target address halt CS7150 -- Fakk 2000 - Computer execution until reset stop Organization - 21
• 22.
  Tracing an Instruction'sExecution Instruction: r3 = r1 + r2 R 0 rs=r1 rt=r2 rd=r3 funct=0 1. Instruction fetch Move instruction address from PC to memory address bus Assert memory read Move data from memory data bus into IR Configure ALU to add 1 to PC Configure PC to store new value from ALUout 2. Instruction decode Op-code bits of IR are input to control FSM Rest of IR bits encode the operand addresses (rs and rt) These go to register file CS 150 - Fakk 2000 - Computer Organization - 22
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  Tracing an Instruction'sExecution (cont’d) Instruction: r3 = r1 + r2 R 0 rs=r1 rt=r2 rd=r3 funct=0 3. Instruction execute Set up ALU inputs Configure ALU to perform ADD operation Configure register file to store ALU result (rd) CS 150 - Fakk 2000 - Computer Organization - 23
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  Tracing an Instruction'sExecution (cont’d) Step 1 CS 150 - Fakk 2000 - Computer Organization - 24
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  Tracing an Instruction'sExecution (cont’d) Step 2 CS 150 - Fakk 2000 - Computer Organization - 25 to controller
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  Tracing an Instruction'sExecution (cont’d) Step 3 CS 150 - Fakk 2000 - Computer Organization - 26
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  Register-Transfer-Level Description Control Transfer data btwn registers by asserting appropriate control signals Register transfer notation: work from register to register Instruction fetch: mabus ← PC; – move PC to memory address bus (PCmaEN, ALUmaEN) memory read; – assert memory read signal (mr, RegBmdEN) IR ← memory; – load IR from memory data bus (IRld) op ← add – send PC into A input, 1 into B input, add (srcA, srcB0, scrB1, op) PC ← ALUout – load result of incrementing in ALU into PC (PCld, PCsel) Instruction decode: IR to controller values of A and B read from register file (rs, rt) Instruction execution: op ← add – send regA into A input, regB into B input, add (srcA, srcB0, scrB1, op) rd ← ALUout – store result of add into destination register CS 150 - Fakk 2000 - Computer (regWrite, wrDataSel, wrRegSel) Organization - 27
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  Register-Transfer-Level Description (cont’d) How manystates are needed to accomplish these transfers? Data dependencies (where do values that are needed come from?) Resource conflicts (ALU, busses, etc.) In our case, it takes three cycles One for each step All operation within a cycle occur between rising edges of the clock How do we set all of the control signals to be output by the state machine? Depends on the type of machine (Mealy, Moore, synchronous Mealy) CS 150 - Fakk 2000 - Computer Organization - 28
• 29.
  Review of FSMTiming fetch decode execute step 1 step 2 step 3 IR ← mem[PC]; A ← rs rd ← A + B PC ← PC + 1; B ← rt to configure the data-path to do this here, when do we set the control signals? CS 150 - Fakk 2000 - Computer Organization - 29
• 30.
  FSM Controller forCPU (skeletal Moore FSM) First pass at deriving the state diagram (Moore machine) These will be further refined into sub-states reset instruction fetch instruction decode SW ADD J instruction LW execution CS 150 - Fakk 2000 - Computer Organization - 30
• 31.
  FSM Controller forCPU (reset and inst. fetch) Assume Moore machine Outputs associated with states rather than arcs Reset state and instruction fetch sequence On reset (go to Fetch state) Start fetching instructions reset PC will set itself to zero Fetch instruction mabus ← PC; fetch memory read; IR ← memory data bus; PC ← PC + 1; CS 150 - Fakk 2000 - Computer Organization - 31
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  FSM Controller forCPU (decode) Operation Decode State Next state branch based on operation code in instruction Read two operands out of register file What if the instruction doesn’t have two operands? Decode instruction branch based on value of decode Inst[15:13] and Inst[3:0] add CS 150 - Fakk 2000 - Computer Organization - 32
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  FSM Controller forCPU (Instruction Execution) For add instruction Configure ALU and store result in register rd ← A + B Other instructions may require multiple cycles add instruction execution CS 150 - Fakk 2000 - Computer Organization - 33
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  FSM Controller forCPU (Add Instruction) Putting it all together and closing the loop the famous reset instruction instruction fetch Fetch fetch decode execute cycle Decode instruction decode instruction add execution CS 150 - Fakk 2000 - Computer Organization - 34
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  FSM Controller forCPU Now we need to repeat this for all the instructions of our processor Fetch and decode states stay the same Different execution states for each instruction Some may require multiple states if available register transfer paths require sequencing of steps CS 150 - Fakk 2000 - Computer Organization - 35