Skip to main content
UploadLanguage (EN)Support
BusinessMobileSocial MediaMarketingTechnologyArt & PhotosCareerDesignEducationPresentations & Public SpeakingGovernment & NonprofitHealthcareInternetLawLeadership & ManagementAutomotiveEngineeringSoftwareRecruiting & HRRetailSalesServicesScienceSmall Business & EntrepreneurshipFoodEnvironmentEconomy & FinanceData & AnalyticsInvestor RelationsSportsSpiritualNews & PoliticsTravelSelf ImprovementReal EstateEntertainment & HumorHealth & MedicineDevices & HardwareLifestyle
Uploaded byRahulRathi94
PPTX, PDF886 views

Lecture 44

This document discusses memory organization and management techniques. It covers memory hierarchy including main memory, auxiliary memory, cache memory and virtual memory. It then describes memory management hardware and its basic functions like dynamic storage relocation and memory protection. The document explains segmentation as a memory management scheme that supports variable sized segments. It provides an example to illustrate segmentation and how multiple users can share segments. Finally, it discusses combining segmentation with paging to create a segmented page system and how page and segment tables are implemented.

Technology◦Education◦
Downloaded 49 times
Memory Organization 1 Lecture 44 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Overview  Memory Hierarchy  Main Memory  Auxiliary Memory  Associative Memory  Cache Memory  Virtual Memory  Memory Mgt Hardware
Memory Organization 2 Lecture 44 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Memory Mgt Hardware Basic Functions of MM - Dynamic Storage Relocation - mapping logical memory references to physical memory references - Provision for Sharing common information stored in memory by different users - Protection of information against unauthorized access Segmentation - A segment is a set of logically related instructions or data elements associated with a given name - Variable size User's view of memory User's view of a program The user does not think of memory as a linear array of words. Rather the user prefers to view memory as a collection of variable sized segments, with no necessary ordering among segments. Subroutine Stack SQRT Main Program Symbol Table
Memory Organization 3 Lecture 44 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Segmentation - A memory management scheme which supports user's view of memory - A logical address space is a collection of segments - Each segment has a name and a length - Address specify both the segment name and the offset within the segment. - For simplicity of implementations, segments are numbered. Segmentation Hardware < Segment Table limit base (s,d) s Memory + y n error CPU
Memory Organization 4 Lecture 44 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Segmentation Example Subroutine Segment 0 Stack Segment 3 SQRT Segment 1 Main Program Segment 2 Symbol Table Segment 4 Segment 0 Segment 3 Segment 2 Segment 4 Segment 1 1400 2400 3200 4300 4700 5700 6300 6700Segment Table 1000 1400 400 6300 400 4300 1100 3200 1000 4700 limit base 0 1 2 3 4 Logical Address Space
Memory Organization 5 Lecture 44 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Sharing of Segmentation Editor Segment 0 Data 1 Segment 1 Logical Memory (User 1) Editor Segment 0 Data 2 Segment 1 Logical Memory (User 2) Editor 43062 Data 1 68348 72773 90003 98556 Data 2 25286 43062 4425 68348 limit base 0 1 Segment Table (User 1) 25286 43062 8550 90003 limit base 0 1 Segment Table (User 2) Physical Memory
Memory Organization 6 Lecture 44 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Segmented Page System Segment Page Word Segment table Page table + Block Word Logical address Physical address
Memory Organization 7 Lecture 44 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Implementation of Page and Segment table Implementation of the Page Table - Hardware registers (if the page table is reasonably small) - Main memory Implementation of the Segment Table Similar to the case of the page table - Cache memory (TLB: Translation Lookaside Buffer) - To speedup the effective memory access time, a special small memory called associative memory, or cache is used - Page Table Base Register(PTBR) points to PT - Two memory accesses are needed to access a word; one for the page table, one for the word
Memory Organization 8 Lecture 44 CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT Example Logical and Physical Addresses Logical and Physical Memory Address Assignment Segment Page Word 4 8 8 Block Word 12 8 Physical address format: 4096 blocks of 256 words each, each word has 32bits 2 x 32 Physical memory 20 Logical address format: 16 segments of 256 pages each, each page has 256words Hexa address Page number Page 0 Page 1 Page 2 Page 3 Page 4 60000 60100 60200 60300 60400 604FF Segment Page Block 6 00 012 6 01 000 6 02 019 6 03 053 6 04 A61 (a) Logical address assignment (b) Segment-page versus memory block assignment