Table 1 Literature survey
Refs. | Authors | Model | Advantages | Disadvantages | Accuracy | Year |
|---|---|---|---|---|---|---|
[1] | Mehedi Hasan, et al. | XOR-XNOR module | Less power consumption, efficiency. Model extending FA up to 32 bits in a ripple carry adder | Couldn’t process multiple inputs to the complex digital circuit | >90% | 2021 |
[2] | Shoba M, et al. | FA in GDI logic | FAs have been cascaded and extended up to 32 bits. | Uses a larger number of transistors to generate the output, which results in more delay. | >85% | 2016 |
[3] | Sanapala K, et al. | Multi Vt & GDI | Utilizes gates with different thresholds to optimize for power, timing, power dissipation and area constraints. Multi-Vth optimization reduced leakage power by a factor of 2-3X with an area variation of plus or minus 2%. | Potential yield loss due to process variations. increased fabrication complexity, longer design times | >82% | 2019 |
[4] | Hassoune I, et al. | FA by Branch Based Logic & PT | An ultralow-power (ULP) cell is described for optimization & tremendous benefit for multiplier application | Design has more PD and PDP and also uses more transistors for single-bit generation. | >78.5% | 2010 |
[5] | Mehedi Hasan, et al. | Comprising an XOR-XNOR module | XOR-XNOR module followed by pass transistors and inverters to generate the sum and carry outputs | Voltage swing | >90% | 2023 |