1 Introduction

The propagation delay of the ripple carry adder is linearly proportional to ‘N’. The adder timing constraint will be given in Eq. 1.

$$\text{t}_{\text{adder}}=\text{(N-1)}\,\text{t}_{\text{carry}}+\text{t}_{\text{sum}}$$
(1)

The carry-bit ripples from one stage to another stage. Due to that, the propagation delay is consistent throughout the circuit, depending on the number of logic stages that must be input to another stage. This dependence creates the wiring capacitance and propagation delay. In the synthesis report, the maximum combinational path delay is based on logic delay and route delay as in Eq. 2.

$$\begin{aligned}\left.\begin{array}{c}\text{Maximum}\\ \text{combinational} \\ \text{path delay} \end{array} \right\} &= \text{logic delay} + \text{net delay}\end{aligned}$$
(2)

The proposed technique reduces logic and route delay by removing undesired paths and destination ports. According to the implementation netlist, the propagation delay is short, measured in nanoseconds or picoseconds. Each gate must stabilize before the following one in the sequence can be read. So, the total time for each gate in the longest possible output sequence is added together to calculate the total delay. Modern integrated circuits (ICs) can have billions of total gates and run at extraordinary speeds. Inconsistent propagation delay in an integrated circuit can result in data errors or race conditions on the chip. As a result, the PD is an essential consideration in high-speed circuit design, as well as a processing speed limiter. As a result, taking into account power delay products is critical for improving circuit accuracy and efficiency.

Sub-threshold current, tunnelling current, and leakage current cause static power dissipation. This dissipation is probably ignored by avoiding idle gates in the circuit. In some situations, both NMOS& PMOS are partially ON and charging/discharging the load capacitor (switching conditions may cause dynamic power dissipation). In sequential circuits, these dissipations are reduced by the clock strategy technique. The combinational circuit is independent of the clock signal for processing the data. So we proposed the Self Switching Adder circuit and implemented that logic in the Count Ones Circuit with the conditional statement to reduce the path delay and power. Regarding the literature survey mentioned in Table 1 below.

Table 1 Literature survey
Full size table
Fig. 1
figure 1

Block diagram of Count One’s Circuit

Full size image

2 Existing techniques for 1-BIT adder design

The challenging factors of speed and power are directly proportional to each other. Reducing the power may affect the Speed of the circuit [6,7,8,9,10]. Tree-structured arithmetic circuits deal with the investigation of area and power delay in the low-voltage concept [6]. To improve the switch delay, they used pass transistor logic (PTL) [11], but it introduced the voltage swing problem in the output node. The conventional method of the XOR gate [1, 5] is used to invert the input. Instead of that, using quantum-dot cellular automata circuit fabrication [12] can identify the missing cells in fabrication & rectify the problem for better performance. FA is a primary block to construct a possible complex system. At maximum time, conventional CMOS has less switching activity [13] due to short circuit current & dynamic current. Most of the complex designs initiate with hybrid structures [14, 15]. However, some of the hybrid designs [16] have less drive capability. For DSP primary portion is FA for arithmetic logic. To get high performance, using Complementary Pass Transistor logic [9,10,11,12,13,14,15,16,17,18] is highly preferable due to the NMOS only present in this technique. But it has a voltage swing at the output node. The default FA design consumes 28 transistors, but the GDI Technique for Energy-Efficient Arithmetic Applications [17] consumes only 10 transistors. It consumes 1.843µW and 0.605ns delay, which is higher than the proposed model. Like the PT-based design [19] of hybrid FA has used 18 T to construct the 4-bit ripple carry adder [20] to perform the low PDP. Another technique refers Transmission gate (TG) for the design hybrid 1-bit adder [14, 21, 22]– [15] to develop the performance of the architecture. Instead of PT and TG for the design of FA, used 1-bit mirror full adder [23] was used to develop the functional application.

Importantly, static and dynamic dissipations [24] are desired for the performance of the digital circuits in VLSI [25, 26]. Some modified FAs using CMOS gates have consumed 6.344µW, which is higher than our proposed technique. These dissipations are probably reduced by reversible logic [27, 28], which is expressed as an N-input pattern*N-output pattern. The above-mentioned efficient designs for digital circuits focused the minimizing power & path delay [12, 29]. Most of the complex circuits are based on simple structures like FA to develop the complex circuit with minimized logic, net delay, and power [30,31,32].

3 Proposed adder design

  1. A.

    Hybrid adder modified expression

The full adder function for inputs A, B, and Cin will be expressed as sum and carry. Propagation delay due to carry in the circuit is considered to attain low power and minimized logic & net delay. Consider the proposed Table 2 for self-switching by the conditional algorithm.

Table 2 Proposed hybrid adder self-switch conditional TT for cin from the previous sequence
Full size table

The proposed Output of the full adder has been expressed as in Eqs. 3 and 4.

$$\displaystyle\mathrm{Sum}=\text{(A + B)}\cdot\, \overline{(A\cdot B)} \oplus \text{C}_{in}$$
(3)
$$\displaystyle\mathrm{Carry} = \bigl(\text{A} \oplus \text{B} \, {\&} \, \text{Cin} \bigr) + \text{(A} {\&}\text{B)}$$
(4)

In the above-mentioned Eqs. 3 and 4, Cin looks ahead for every Boolean expression to sort out a problem of dissipation due to idle and data path delay.

  1. B.

    Conditional statement for self-switch hybrid adder

  1. i.

    In Eqs. 3 and 4, the previous sequence of Cin plays the major role in the function of sum and carry.

  2. ii.

    In Eqs. 3 and 4, we observed that the output of XOR1 & AND1 does not depend on the previous sequence Cin to produce the output. So, not bothered gate delay over here.

  3. iii.

    In Table 1, the dependent function is assigned with two conditional inputs of Cin = 0 & Cin = 1.

  4. iv.

    When Cin is zero, the output function of AND2 will be disabled and remain zero until Cin changes to one. So proposed method uses a conditional statement to bypass the AND2 function and set zero as one of the reference inputs to the OR gate to produce the Carry.

  5. v.

    When Cin is one, XOR1 output further decides to pass the next stage input of XOR2 &AND2 is dependent on the self-switch by the conditional algorithm. Here proposed algorithm stops the propagation bit from XOR1 to XOR2 & AND2 (bypassed). It sets the previous register value as a reference input for generating the sum and carry.

  6. vi.

    Self-switching will be activated automatically according to the previous sequence Cin.

  7. vii.

    The conditional algorithm will take care of the self-switching for a 1-bit adder or conditional adder, which reduces the maximum combinational path delay and power consumption

C. Condition software implemented operation for self-switch full adder

The following statements are according to Eq. 2, where idle gates create power dissipation and more path delay. Here, A, B are independent inputs, and Cin is dependent on the previous sequence.

  1. i.

    When independent input A = B = 1.

\(\text{Carry} = \left\{ {\begin{array}{*{20}c} {1;} & {{\text{Cin}} = 0} \\ {1;} & {{\text{Cin}} \ne 0} \\ \end{array} } \right.\) 

  1. ii.

    When independent input A = B = 0.

\(\text{Carry} = \left\{ {\begin{array}{*{20}c} {0;} & {{\text{Cin}} = 0} \\ {0;} & {{\text{Cin}} \ne 0} \\ \end{array} } \right.\) 

  1. iii.

    When independent input is a variation.

\(\text{Carry} = \left\{ {\begin{array}{*{20}c} {0;} & {{\text{Cin}} = 0} \\ {1;} & {{\text{Cin}} \ne 0} \\ \end{array} } \right.\) 

Let’s explain the brief operation of a few functions for a clear understanding. Consider both independent input A = B = 0 & dependent previous sequence input Cin = 0. For these inputs, RTL_XOR1 passing the output is 0, this output further decides to pass the next stage input of RTL_XOR2 & RTL_AND2 are dependent on the self-switch by the conditional algorithm. Here proposed algorithm passes the RTL_XOR1 output to the RTL_XOR2 to generate the sum & sets 0 as one of the reference inputs to the OR gate for carry generation.

Consider both independent input A = B = 0 & dependent previous sequence input Cin = 1. For these inputs, RTL_XOR1 passes the output of 0, which further decides whether to pass the next stage input. RTL_XOR2 & RTL_AND2 are dependent on the self-switch controlled by the algorithm. In the proposed conditional algorithm, set 0 as one of the reference inputs to the OR gate for carry generation.

Consider independent input A = 1 & B = 0, dependent previous sequence input Cin = 0. For these inputs, RTL_XOR1 passes the output is 1. This output further decides to pass the next stage input of RTL_XOR2 & RTL_AND2 are dependent on the self-switch by the algorithm. Here proposed algorithm passes the RTL_XOR1 output to the RTL_XOR2 to generate the sum and sets 0 as one of the reference inputs to the OR gate for carry generation.

Consider independent input A = 1 & B = 0, dependent previous sequence input Cin = 1. For these inputs, RTL_XOR1 passes the output of 1, which further decides whether to pass the next stage input. RTL_XOR2 & RTL_AND2 are dependent on the self-switch controlled by the algorithm. Here proposed algorithm passes the RTL_XOR1 output to the RTL_XOR2 to generate the sum and sets 1 as one of the reference inputs to the OR gate for carry generation. Here proposed algorithm ignore the AND2 function by set the logic one of the reference inputs to the OR gate for carry generation. These reference input based in Cin (except A = B = 0) by conditional algorithm. The proposed Count Ones architecture in Fig. 1 uses self self-switching 1-bit adder with a conditional algorithm to analyse the combined adder functionality with path delay and power consumption. The output of the architecture in Fig. 1 is based on carry [4], sum [4] and sum [3].

Fig. 2
figure 2

Proposed Full Adder Logical Timing Diagram

Full size image

4 Results and discussions

The proposed method’s overall on-chip power is 9% lower than the conventional full adder [1] logic in the Table 3.

Table 3 Total On-chip power for the conventional and the proposed adder
Full size table
Fig. 3
figure 3

Self-Switch Full Adder Conditional Timing Diagram

Full size image

In this, ideal logic in the Fig. 2 create the worst-case delay, but this can be ignored by reduced path delay, and dynamic dissipation is presented in the Table 3. The above condition in Fig. 3 is applicable for reducing path delay which has dependent input in the generation of sum, it can apply to reducing path delay and consideration of overall power performance is very less in the synthesis netlist and the same exposed in Register Transfer Logic (RTL).

The total data path delay and power decrement in the proposed method are based on the dependent previous sequence Cin (Table 4). Self-switching method setting zero as one input by wire will reduce the logic and route delay (Fig. 2).

Table 4 Data path delays for the conventional and the proposed full adder
Full size table

The total data path delay and power decrement in the proposed method are based on the dependent previous sequence Cin (Table 4). Self-switching method setting zero as one input by wire will reduce the logic and route delay (Fig. 2). Similarly, mimic is characterised by an conditional algorithm to set zero, for Cin = 0 to the OR gate for generating the carry with minimal delay and no slack in the functional output. The self-switching method probably reduces the expected time to perform the function. Similarly above tasks have been reduced in the proposed method based on the dependent previous sequence Cin. Self switching stops propagating the bit from RTL_XOR1 to RTL_XOR2 & RTL_AND2. It sets the previous register value as a reference input for generating the sum and carry.

It sets the previous register value (Cin) as a reference input to that for generating sum and carry to the OR gate for generating the carry with minimal delay and no slack in the functional output (Fig. 3). The proposed Self-switching method probably reduces the expected time to perform the function than Cin = 0 & 1. Its path delay and power performance are 25% and 18% better (Fig. 4) than the conventional full adder [2]. The same power and path delay achieved logic will be implemented in the count one’s circuit as in Fig. 1, and analyze the performance between proposed and conventional methodologies.

Fig. 4
figure 4

Total on-chip power and maximum combinational path delay analysis

Full size image

To achieve high performance, concentrate the path between FA1 to FA4, FA3 to FA4, and FA2 to FA4. Because FA4 variables A and B fully depend on the carry-out of FA1, FA2& FA3. Similarly, FA3 variables A & B depend on the sum of FA1 & FA2. In Fig. 1, inputs may be assigned in coding directly or set in the test bench. According to that proposed self-switching, FAs in count one’s circuit follow the Cin = 0 or 1 condition statement to produce the reduced path delay and power. Let’s consider FA’s input is X = 1,011,101, here X0 passes to Cin3, X1 passes to Cin1, and X4 passes to Cin2.

In Figs. 5 and 6; Tables 5 and 6, the LUT concept has been approached in the proposal, which is the primary block for FPGA & used to implement the conditional logic function of N-Boolean variables. According to this concept, proposed counting one’s circuit consumes 25% less power than the conventional method.

Fig. 5
figure 5

On-chip component power analysis

Full size image
Table 5 POWER: On-chip components for conventional VS proposed count one’s logic circuit
Full size table
Table 6 Proposed count one’s circuit path delay
Full size table
Table 7 Performance analysis of the full adder
Full size table
Fig. 6
figure 6

Count one circuit with different path delay analyses

Full size image
Fig. 7
figure 7

Performance analysis of the proposed hybrid full adder with existing methods (a) Power analysis (b) Delay analysis (c) Power delay product analysis

Full size image
Fig. 8
figure 8

Count one circuit on-chip power analysis

Full size image

Path delay for count one’s circuit with self-switch logic is described in Table 6. Descriptions of paths are, Path1 from A [2] to carry [3], path 2 from A [2] to sum [4], path3 from A [2] to sum [3], path 4 from A [2] to carry [4], path 5 from A [1] to carry [1], path 6 from A [2] to sum [2], path 7 from A [1] to sum [1] and path 8 from A [2] to carry [2]. After path delay analysis, we concluded our device (Fig. 1) would reduce by around 14% of path delay and proposed that FA reduces to 17% of the power delay product (PDP) than conventional methods [1]. Proposed count one circuit output based on carry [4], sum [4], and sum [3], and our design functional output is 101(5) for the given input 1,011,101. Performance analysis of the full adder in the aspect of Power, Path delay & PDP in Table 7; Figs. 7 and 8.

5 Conclusion

In this work, both conventional and proposed hybrid adder and Count one’s circuits are simulated with Xilinx Vivado. The proposed full adder by self-switch logic with conditional algorithm synthesis report shows that the reduction of the on-chip power consumed is 0.872µW, and its path delay is reduced from 35.6ps to 32.396ps, which is 9% reduced than the existing [1]. Achieved Dynamic power is less than 9% the Hybrid 1-bit adder. Construct and implement Count One’s circuit by the success of the proposed hybrid full adder as a block, power attainment on the chip is 3.488µW, which is 25% less than the Conventional Full adder. Similarly, the proposed Count One’s circuit, using the Self Switching Full Adder path delay, is reduced further to around 14%.