#

icarus-verilog

Here are 188 public repositories matching this topic...

olofk / edalize

An abstraction library for interfacing EDA tools

fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass

Updated Aug 12, 2026
Python

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Sep 3, 2026
Verilog

mshr-h / vscode-verilog-hdl-support

Verilog/SystemVerilog support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Sep 8, 2026
TypeScript

wyvernSemi / pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

c verification verilog virtual vivado modelling icarus-verilog ghdl cosim pcie pli bfm verilator nvc xsim questa-sim

Updated Jun 16, 2026
C

neorv32-verilog

stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Dec 3, 2025
VHDL

scarv / xcrypto

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Jan 5, 2023
Verilog

unixb0y / SystemVerilogSHA256

SHA256 in (System-) Verilog / Open Source FPGA Miner

fpga bitcoin mining verilog sha256 systemverilog icarus-verilog

Updated Mar 10, 2018
SystemVerilog

dpretet / svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator surfer svut

Updated Oct 22, 2024
Python

sgherbst / svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

erfnzdeh / verilog-fpga-parking-management-system

Synthesisable Verilog controller for a 700-space university car park: independent occupancy and availability tracking for university and visitor vehicles against one shared capacity, with a transcript-generating testbench and an Intel Quartus project.

fpga rtl verilog icarus-verilog hdl modelsim testbench digital-design quartus sharif sharif-university intel-fpga hardware-design

Updated Aug 12, 2026
Verilog

albertxie / iverilog-tutorial

Quickstart guide on Icarus Verilog.

verilog signal icarus-verilog gtkwave csc258

Updated Jun 18, 2020
Verilog

Varunkumar0610 / RISC-V-32I-5-stage-Pipeline-Core

Implementation of 5 Stage 32I RISC V Pipeline Processor.

pipeline visual-studio-code riscv verilog icarus-verilog gtkwave

Updated Sep 6, 2024
Verilog

wyvernSemi / usbModel

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

usb vhdl verilog vivado systemverilog icarus-verilog ghdl nvc xsim cosimulation cmodel questa-sim

Updated Oct 15, 2024
C++

yasnakateb / PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm cpu verilog icarus-verilog verilog-hdl iverilog arm-processor arm-pipeline

Updated Mar 21, 2022
Verilog

wyvernSemi / tcpIpPg

10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL

simulation verification verilog vivado ethernet icarus-verilog ghdl tcp-ip verilator nvc 10g xsim virtual-processor xgmii questa-sim

Updated Jan 28, 2025
C++

EDAcation / vscode-edacation

VS Code extension for EDAcation - Learning environment for digital hardware design.

vscode eda vscode-extension icarus-verilog hdl yosys iverilog nextpnr openfpgaloader

Updated Jul 6, 2026
TypeScript

sifferman / fusesoc_template

Example of how to get started with olofk/fusesoc.

vivado icestorm icarus-verilog yosys fusesoc tinyfpga-bx nexys-a7 nextpnr-ice40

Updated Jul 25, 2021
Python

msinger / dmg-sim

SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip

nintendo asic gameboy simulation electronics verilog chip systemverilog game-boy icarus-verilog dmg-001 dmg-cpu

Updated Sep 9, 2026
SystemVerilog

Alfredosavi / tangnano-hello

Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

docker open-source opensource fpga makefile hello-world blink icarus-verilog gtkwave blinky yosys icarus gowin sipeed nextpnr apicula tangnano tangnano9k openfpgaloader sipeed-tang-nano-9k

Updated Jul 26, 2024
Makefile

aditeyabaral / DDCO-Lab-UE18CS207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

Updated Apr 17, 2020
Verilog

Add this topic to your repo

To associate your repository with the icarus-verilog topic, visit your repo's landing page and select "manage topics."