Fix binary use of reduction NAND and NOR - #2590
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Updated the ivtest smoke-test expectations to account for the 7 files that intentionally use Icarus Verilog’s non-standard binary |
| ExpectedFailCount[syntax:ivtest]=116 | ||
| ExpectedFailCount[lint:ivtest]=116 | ||
| ExpectedFailCount[project:ivtest]=145 | ||
| ExpectedFailCount[syntax:ivtest]=123 |
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I wonder if the test that is now failing was using that as a negative example or if iverilog indeed supports this as binary operator, did you dig into the example ?
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I do like to support a super-set of Verilog if there is any verilog parser that supports this particular feature (but I don't remember what original was supporting it, maybe @fangism knows). The problem with taking it out of the grammar is, that it then will be a hard failure and prevent the parser to recover after that. Ideally we would like to introduce some 'soft' failure where we parse this, but fail with an error but then continue parsing to find potentially other issues. I need to think about the details, so will leave this PR open for now while that is settled. |
Addresses #2568 by removing the binary operator grammar rules for
~&and~|, which are valid only as unary reduction operators. Adds regression tests to verify that their invalid binary usage is rejected.