[BUG] Add error on binary use of unary reduction operator ~| and ~& #2568

Verible verision
commit: 7807ee1

Describe the bug

Verible accepts the expression var1 ~| var2 and var1 ~& var2 without reporting a syntax error.
In SystemVerilog, ~| is a unary reduction NOR operator, not a valid binary infix operator.
Therefore, var1 ~| var2 should be rejected, but Verilator appears to parse and accept it.

To Reproduce

module bug_reduction_nor_binary (
    input  logic [3:0] var1,
    input  logic [3:0] var2,
    output logic [3:0] out
);

    // BUG: ~& and ~| is a unary reduction operator, not a binary infix operator
    assign out = var1 ~& var2;
    assign out = var1 ~| var2;
    
endmodule

command
verible-verilog-syntax minimal.sv

Actual behavior:

Nothing happen, no warnings or errors.

Expected behavior

decline this syntax