Verilog HDL

Verilog HDL

• 2.
  Table of Contents 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Verilog data types 7. Abstraction 8. Gate level Abstraction 9. Data flow level Abstraction 10. Behavioral level Abstraction 11. Switch level Abstraction 12. Advance verilog Keywords
• 3.
  Welcome to verilog 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Verilog data types 7. Abstraction 8. Gate level Abstraction 9. Data flow level Abstraction 10. Behavioral level Abstraction 11. Switch level Abstraction 12. Advance verilog Keywords
• 4.
  Introduction to VLSI •Small scale integration (SSI) 1 – 10 gates • Medium Scale Integration (MSI) 10 – 100 gates • Large Scale Integration (LSI) 100 – 1000 gates • Very Large Scale Integration (VLSI) 1000 – 100000 gates • Ultra High Scale Integration (ULSI) > 100000 gates
• 5.
  Design Flow inVLSI Design Specification Behavioral Description RTL Description Logical Synthesis/ Timing Verification Gate level Netlist Semi Custom Design Floor planning Placement & Routing Full Custom Layout Physical Verification IMPLEMENTATION Gate level Simulation Functional Verification Layout Verification
• 6.
  Table of Contents 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Verilog data types 7. Abstraction 8. Gate level Abstraction 9. Data flow level Abstraction 10. Behavioral level Abstraction 11. Switch level Abstraction 12. Advance verilog Keywords
• 7.
  Introduction to VerilogHDL • Programming language. • Hardware Description Language. • Understand the Behavior of Hardware. • Its syntax are similar to C language. • Easy to Learn & Use. • The Verilog HDL is both a behavioral and structural language. • Verilog is case sensitive language.
• 8.
  Models in Verilog •Models in the Verilog HDL can describe both the function of a design and the components . • It can also define connections of the components in the design.
• 9.
  Welcome to verilog 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Verilog data types 7. Abstraction 8. Gate level Abstraction 9. Data flow level Abstraction 10. Behavioral level Abstraction 11. Switch level Abstraction 12. Advance verilog Keywords
• 10.
  History • Verilog wasinvented by Phil Moorby and Prabhu Goel in 1983/1984 at Gateway Design Automation • GDA was purchased by Cadence Design Systems in 1990. • Originally, Verilog was intended to describe and allow simulation. • Later support for synthesis added.
• 11.
  History (cont…) • Cadencetransferred Verilog into the public domain under the Open Verilog International (OVI). • Now it is known as Accellera organization. • Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.
• 12.
  • Verilog 2001Extensions to Verilog-95 were submitted back to IEEE to cover few limitation of Verilog -95. • This extensions become IEEE Standard 1364- 2001 known as Verilog-2001. History (cont…)
• 13.
  • Verilog-2001 isthe dominant flavor of Verilog supported by the majority of commercial EDA software packages. • Today all EDA developer companies are using Verilog - 2001 History (cont…)
• 14.
  • Verilog 2005Don’t be confused with System Verilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections. • A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modeling with traditional Verilog. History (cont…)
• 15.
  • System Verilogis a superset of Verilog- 2005, with new features and capabilities to aid design-verification and design-modeling. • As of 2009, the System Verilog and Verilog language standards were merged into System Verilog 2009 (IEEE Standard 1800- 2009). History (cont…)
• 16.
  History (cont…) • Theadvent of hardware verification languages such as Open Vera, System C encouraged the development of Superlog by Co-Design Automation Inc. • Co-Design Automation Inc was later purchased by Synopsys. • The foundations of Superlog and Vera were donated to Accellera, which later became the IEEE standard 1800-2005: System Verilog.
• 17.
  Continues to verilog 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Verilog data types 7. Abstraction 8. Gate level Abstraction 9. Data flow level Abstraction 10. Behavioral level Abstraction 11. Switch level Abstraction 12. Advance verilog Keywords
• 18.
  Design Methodology • Basedon Design Hierarchy • Based on Abstraction Full Adder Full Adder Full Adder Full Adder s0s1s2s3 A B A B A B cico A3 B3 A2 B2 A1 B1 A0 B0 A B cicici co co co
• 19.
  Based on DesignHierarchy o Top Down Methodology. o Bottom Up Design Methodology. FA FA FA FA s0s1s2s3 A B A B A B cico A3 B3 A2 B2 A1 B1 A0 B0 A B
• 20.
  Top Down DesignMethodology Top Level Block Sub Block 1 Sub Block 3 Sub Block 2 Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell
• 21.
  Top Level forFour Bit Ripple carry Counter CLk Reset T_FF tff0 T_FF tff1 T_FF tff2 T_FF tff3 Q Q Q Q Q0 Q1 Q2 Q3
• 22.
  Top Down Method RippleCarry counter T_FF (tff0) T_FF (tff2) T_FF (tff1) D_FF Inverte r D_FF Inverte r D_FF Inverte r T_FF (tff3) D_FF Inverte r
• 23.
  Verilog Code ForRipple Carry Counter module ripple_carry_counter(clk,reset,q); // starting of the module input clk; // Input signal input reset; // Input signal output [3:0] q; // counter output // to the external world T_FF tff0 (q[0],clk,reset); // instantiation of T_FF T_FF tff1 (q[1],q0,reset); // instantiation of T_FF T_FF tff2 (q[2],q1,reset); // instantiation of T_FF T_FF tff3 (q[3],q2,reset); // instantiation of T_FF endmodule // end of module
• 24.
  Lower level module moduleT_FF(clk,reset,q); // starting of the module input clk; // T_FF Input signal input reset; // T_FF Input signal output q; // T_FF output // to the external world wire d; // internal signal D_FF dff0 (q,clk,reset,d); // instantiation of D_FF not n1 (d , q) ; // instantiation of Not Gate endmodule // end of module
• 25.
  Lowest level forCounter Module D_FF(clk,reset,q,d); // starting of the module input clk, d; // Input signal input reset; // Input signal output q; // D_FF output // to the external world always @(posedge clk , negedge reset) if (!reset) // main body of the D_FF q <= 1’b0; // Behavioral level code for D_FF else q <= d; endmodule // end of module
• 26.
  Top Down Method RippleCarry counter T_FF (tff0) T_FF (tff2) T_FF (tff1) D_FF Inverte r D_FF Inverte r D_FF Inverte r T_FF (tff3) D_FF Inverte r
• 27.
  Bottom Up designMethodology Top Level Block Sub Block 1 Sub Block 3 Sub Block 2 Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell
• 28.
  Based on Abstraction •Behavioral Level • Data flow Level • Gate level • Switch level Input outpu t Q=dD=in
• 29.
  Based on Abstraction BehavioralLevel Data flow Level Gate level Switch level count<= count + 1; assign a = b&c and a1(y1,a,b); or o1(y2,c,d); or o2(y,y1,y2); pmos p1 (out,pwr,in); nmos n1 (out,gnd,in);
• 30.
  Continues to verilog 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Verilog data types 7. Abstraction 8. Gate level Abstraction 9. Data flow level Abstraction 10. Behavioral level Abstraction 11. Switch level Abstraction 12. Advance verilog Keywords
• 31.
  Module • This isthe basic building block of Verilog. • Followed by the name of the Design. • The Body of the Design is Enclosed inside the module. • Module is ended by the keywords endmodule
• 32.
  Module Structure Declaration ofwire and reg variables Instantiation of other module Continuous statements or Data flow statement Procedural block Always or initial block Task and functions endmodule Module name portlist , port declaration parameter declarations Module BODY Module STARTING Module ENDING
• 33.
  Example of module moduletest (output y,input a,input b) ; assign y = a&b; initial begin $display("Hello world welcome to VLSI"); $finish; end endmodule Module starting Module name Body Ending of the module Port list
• 34.
  module ripple_carry_counter(clk,reset,q); input clk,reset; output[3:0] q; T_FF tff0 (q[0],clk,reset); // instance module name must be same as // declared in s main module endmodule Instantiation • The Word Instantiation means to transfer. • Transfer > transfer the property of Design • Instantiation is a process to create an object for the Design which will replicate its all property where it is instantiated. instantiation instance name Port list D_FF Inverter Ripple Carry counter T_FF tff0
• 35.
  Instantiation methods • NamedBased • Ordered Based // this is half adder verilog code module half_adder (S, C , A, B ) // module name & port declaration output S; // output port declarations output C; // output port declarations input A; // input port declarations input B; // input port declarations xor x1 ( S, A, B); // instantiation of xor gate and a1 (C, A, B); // instantiation of and gate endmodule
• 36.
  Instantiation • Named Based //This is Full adder verilog code module Full_adder (SUM, Cout, P,Q,Cin) output SUM , Cout; //output ports input P,Q, Cin // input ports wire s1, co1 ,co2; half_adder H1 (.S1(S), .Co1(C) , .P(A),.Q(B)) // ports are connected by half_adder H2(.SUM(S), .Co2(C),.S1(A) ,.Cin(B)) ; // name to each signal or o1 ( Cout,Co1,Co2); Endmodule //module half_adder ( S, C , A, B )
• 37.
  Instantiation • Ordered Based //This is Full adder verilog code module Full_adder (SUM, Cout, P,Q,Cin) output SUM , Cout; //output ports input P,Q, Cin // input ports wire s1, co1 ,co2; half_adder H1 (S1, Co1 , P,Q) ; // ports are connected by the same half_adder H2(SUM, Co2,S1 ,Cin) ; // Order as these are defined in main module or o1 ( Cout,Co1,Co2); endmodule // module half_adder (S, C , A, B )
• 38.
  Input Output Ports •I/O ports are the signal to interface with the external World. • In verilog any module support three types of ports. – Input – Output – Inout moduleInput port Output port . inout port
• 39.
  Port Connection Rules •Input ports should be always wire & can be connected to net as well reg to the External World • Inout ports are always net type in both the module Internal as well as External . • Output ports may be reg as well wire or net internally but should be connected to net only • Width Matching: suppose you defined any port with multi bits then at the time of interconnection both the data width must be same. • If it is single bit then no need to declare bit size. Input Output inout reg or net reg or netnet net net net EXTERNAL MODULE OR STIMULUS INTERNAL MODULE
• 40.
  Stimulus 1. To checkthe functionality of the main design we require certain value of the input signal. 2. To model these input value we will use the Stimulus block. 3. This is same as test bench. 4. In this module we provide the input to the design module and check its response back to the stimulus. 5. The stimulus coding is written in verilog code. DESIGN MODULE Input port O/PStimulus
• 41.
  Stimulus module and_gate(Y,A,B); output Y; inputA,B; and a1 ( Y , A , B); endmodule AND GATE DESIGN MODULE Y And gate Stimulus A B module stimulus_and_gate; reg A,B;; wire Y; and_gate and1 (Y,A,B); // //instantiation of design initial // stimulus generator begin $monitor (“ %b”, Y); A=1’b0; B=1’b0; #10 A =1’b0; B=1’b1; #10 A=1’b1; B=1’b0; #10 A=1’b1; B = 1’b1; end endmodule
• 42.
  Continues to verilog 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Lexical Conventions 7. Verilog data types 8. Abstraction 9. Gate level Abstraction 10. Data flow level Abstraction 11. Behavioral level Abstraction 12. Switch level Abstraction 13. Advance verilog Keywords
• 43.
  Lexical Conventions • Touse lexical convention following option can be used. – b Blank Space – t Tab Space – n New line • Comments – // this is comment line //single line Coment – /* this is multi line comment // Multi line Comment /* – This is multi line comment */ // Multi line Comment */ • Escape character : escape character begin with the character to escape the property of any wildcard character. – ** // escape the property of *
• 44.
  Lexical Conventions • Operator –Three types of operator is supported in verilog – Unary, binary & ternary. A = ~ B ; // unary operator A = B & C; // binary operator A = B ? C : D; //ternary operator
• 45.
  Lexical Conventions • NumberSpecification: Sized Number – <size > ‘ < base > < number >; – Size is the size of the identifier. – Base is the base like binary or decimal. – Number is the value of the identifier. – 8 ’ b0110011; // this is 8 bit binary value – 128 ‘ d 567; ; // this is 128 bit decimal value – 32 ‘ h 783; // this is 32 bit hexadecimal value – 64 ‘ o 3432; // this is 64 bit octal value
• 46.
  Lexical Conventions • NumberSpecification : Unsized Number : • without declaring the size of the identifier size is Macine dependence or 32/64 bit by default. – ‘h 892; // Machine dependent / 32 bit // hexadecimal data • Similarly the default base format is decimal. – Number = 23; //decimal number 32 bit width
• 47.
  Lexical Conventions • Underscorecharacter: – Underscore ( _ ) can be place in between the digit of the number. – Dat a = 16 ‘ b 1001_1010_1110_0001; – Note: never put the starting digit as underscore. • Strings : – Verilog support string type data assignment and treated as ASCII character. – But there is no data type for string. – String must be enclosed inside double inverted commas “ “. – VAR = “ Hello world this is my first String”; // this is string
• 48.
  IDENTIFIER • An identifieris any sequence of letters, digits, dollar signs ($), and underscore (_) symbol, except that: – the first must be a letter or the underscore. – the first character may not be a digit or $. – Upper and lower case letters are considered to be different. – Identifiers may be up to 1024 characters long. – Some Verilog-based tools do not recognize identifier characters beyond the 1024th as a significant part of the identifier. – Escaped identifiers start with the backslash character () and may include any printable ASCII character. – An escaped identifier ends with white space. – The leading backslash character is not considered to be part of the identifier.
• 49.
  Continues to verilog 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Lexical Conventions 7. Verilog data types 8. Abstraction 9. Gate level Abstraction 10. Data flow level Abstraction 11. Behavioral level Abstraction 12. Switch level Abstraction 13. Advance verilog Keywords
• 50.
  Verilog data types •What is data? • What is strength? • What is type? • In verilog there are some codes that perform some data calculation or manipulation. • To store this data we require some variable . • These data storage variable are known as Identifier. • On the basis of the data storage, these variable have some data types.
• 51.
  • Single bitfour valued data. • Multibit What is data? 1 0 X Z 8’b11001101 Integer 231 Real 231.43 Logic One Or True Condition Logic Zero Or False Condition Unknown value High Impedence
• 52.
  What is strength? •The driving strength of a continuous assignment can be specified by the user. • If two signal are driving the same net then the driving strength can be applied to get the require output. Y Y1 Y2 supply 1 driving strong 1 driving pull 1 driving large 1 driving weak 1 driving medium 1 driving small 1 driving highz 1 high impedance highz1 high impedance small0 strong medium0 strong weak0 strong large0 strong pull0 strong Strong0 strong Supply0 strong Weakest 1 Weakest 0 Strength level Degree Strength Type
• 53.
  What is type? •Nets : • A net is declared as wire. • Wire means a wire connection between two gates or hardware. • The output of one logic goes to input of another logic. • In verilog the default declaration of any variable is of net type. • A net does not store a value (except for the trireg net. • it must be driven by a driver, such as a gate or a continuous assignment a b c d y1 y2 Y module logic_wire(Y,a,b,c,d) output Y ; input a , b , c , d; wire y1 , y2 ; and a1 ( y1 , a , b ); or o1 (y2 , c , d); assign Y = y1 | y2; endmodule
• 54.
  Verilog data types: Nets • it must be driven by a driver, such as a gate or a continuous assignment. • If no driver is connected to a net, its value will be high- impedance (z). • Multi bits wire • wire [31:0] data_bus32;
• 55.
  Advanced Net Types •tri: it is similar to wire as syntax wise as well as functionally. • The only difference between wire and tri is wire denote single driver while tri means multiple driver. y module mux(y,A,B,ctrl); output y; input A,B,ctrl; tri y; wire A,B,ctrl; buffif0 bf0 ( y , A , ctrl); buffif1 bf1 ( y , B , ctrl); endmodule B y ctrl y ctrl A y
• 56.
  Advanced Net Types •trireg : trireg is same as wire except that when the net having capacitance effect. • Capacitance effect means it will store the previous value. • Therefore trireg works on two state. • Driven state: when the driver net having a value 1 ,0 ,X then the driven net will follow the driver net. • Capacitance state: when the driver net is unconnected or having a value of Z or high impedance then the driven net will hold the last value. • Ex : buffif1 b1 ( y , A, ctrl); // net y get value whenever the value of A // when ctrl is high. Store the last value when // ctrl is low. Driver net Driven net ctrl
• 57.
  Advanced Net Types •tri0 & tri1: tri0 & tri1 are resistive Pulldown and pullup devices. • When the value of the driving net is high then driven net will get a value of the input . • When the value of the driving net is low the driven net get a value of pulldown or pullup. • Ex : tri0 y; • buff bf0 ( y ,A,ctrl); // when ctrl is high y = A; • // when ctrl is low y = 0; instead of high impedence. • supply0 & supply1: these are used to model the power and Ground. • supply1 VDD; • supply 0 GND;
• 58.
  Advanced Net Types •wor, wand,trior & triand: • When one single net is driven by two net having same signal strength then it is difficult to determine the output on the driven net. • In this case we can use the output oring or anding on both the driving nets. • wor Y ; // or gate for Y1 & Y2 • wand Y; // and of Y1& Y2 • wor : or gate on the output driving nets. • wand : and gates on the output driving nets. Y Y1 Y2 Y Y1 Y2 Y Y1 Y2
• 59.
  Verilog data types •Registers • A register is an abstraction of a data storage element. • A reg variable can be assign by another value only inside the procedural block. • It is not always true that reg variable will infer a FF. Sometime it infer Combo logic. • Registers can be assigned negative values. • When a register is an operand in an expression, its value is treated as an unsigned (positive) value. • reg is the keyword for the register data type.
• 60.
  Verilog Register datatype Declaration reg <signed> <range> <list_of_register_variables> ; reg data; // single bit variable. reg signed [7:0] data_bus. // multiple bits signed variable reg [7:0] data_bus; // multi bits unsigned variable Integer: This is a general reg type variable. Used to manipulate mathematical calculation.  This is integer 32 bit long signed number. integer data; // 32 bit signed value Default value
• 61.
  Verilog Register datatype • real: This is real register data types. Real data type variable has no range. • Default value for real type variable is zero. • real data = 3.34; • real data= 2e10; // 3 * 10 ^6 • NOTE: Real value can not be passed from one module to another in verilog. • time: the simulation is done with respect to time. • To store the time we can use the time type variable. • $time is used to see the system time. It is 64 bits integer type. • $stime is use to display the simulation time & it is 32 bit integer type. • $realtime is real value and it is 64 bits long.
• 62.
  Verilog data types •Vectors: all the data types variable can be declared as multi bits. • If the bit width is not specified then the bit width is one bit. • reg data; // single bit variable • reg [7 : 0 ] data_bus; // multi bits data • wire data; // data is single • wire [7 : 0 ] data_bus; // data_bits multi bits
• 63.
  Verilog Vector datatype • Vector bit select: reg [31 : 0 ] data; bit_select = data [ 7]; • Vector part select: reg [31 : 0 ] data; part_select = data [ 7:0]; reg [0 : 31] data_bus; part_select = data_bus[0:7]; • Variables Vector part select: variabe_name [ < starting_bit> + : width ] byte_select= data_bus [ 16+ : 8 ]; // starting from 16 to 23 variabe_name [ < starting_bit> -: width ] byte_select= data_bus [ 16- : 8 ]; // starting from 9 to 16
• 64.
  Verilog data type •Arrays: • Array is a collection of similar data types. • Array can be multi dimensions. • Declaration of array is similar to C language. • reg array_data [ 7 : 0 ] [ 15 : 0 ]; // two dimension array. • reg [7:0 ] mult_bits_array [7 :0]; // Single dimension array with each // element having 8 bits of data. • integer data_bus[31:0] // 32 variable data_bus • NOTE: Array can not be passed from one module to another in verilog.
• 65.
  Verilog data type •Memories: • Memories: Memory can be model as defining them multi bits array. • reg mem_data [0: N-1]; • Parameter Parameter: To declare constant values in verilog we can used data type of parameter. parameter Data_width=8; // this type of parameter global in nature and can be override at the simulation or from other module. localparam: This is same as parameter expect that other module can not overwrite the constant value from outside of the module localparam DW= 32; Location 0 Location 1 Location 2 Location N-3 Location N-2 Location N-1 MEMORY
• 66.
  Verilog system task •Verilog provide standard system task to perform some routine operation. • These system task start with a character $(keyword). • These routine are used to display output values to the terminal or to display simulation time ect. • ex: $display • $monitor • $strobe • $write • $time • $finish • $recordfile • $dumpfile
• 67.
  Verilog system task •Display Information: • In verilog there are four types of representation • These value can be displayed in binary, hexadecimal, decimal or octal. %d or %D display in decimal % b or %B display in binary %s or %S display string %o or %O display in octal %h or %H display in hexadecimal %c or %C display ASCII character %m %M display hierarchy name %v or %V display strength %t or %T display current time format %e or %E display real number in scientific %f or %F display real number in decimal %g or %G display real number in Format Display Action
• 68.
  Verilog system task •Displaying task : $display • $display(“hello world welcome to VLSI % b” , data); • The above system task will display the string as well the value of the variable in binary format. • Whenever this system task is used in the program it will display according to the variable and the string values & then it bring the Cursor to next line automatically. • $write : it is same like $display except the cursor will remain in the same line at end of the system task. • $write (“%d”,a); // display the value of a in decimal and remain in the same line.
• 69.
  Verilog system task •Displaying task : $monitor • This system task is used as same as $display but it will keep monitoring the value whenever the value of the variable will change. • $monitor (a,b,c); // it will display in decimal whenever the value of the any of the variable will change. • $monitoron is used to enable the system task. • $monitoroff is used to disable the system task. • Displaying task : $strobe • $strobe is same as display except that it will display the value at the end of the simulation time. • $strobe(“%h”, a); // will display the value of a in hex at the end of simulation time.
• 70.
  Verilog system task •Simulation control task $stop: • It will stop the simulation at the given simulation time and provide control to the user to an interactive mode. • #200 $stop // stop the simulation at the 200 time unit . • Simulation control task $finish: • It will terminate the simulation at the given simulation time. • # 500 $finish; // terminate the simulation at the 500 time unit.
• 71.
  Verilog Compiler directive •Compiler directive: compiler directive are defined in verilog as macro. • These macro has certain property and the effect of these macro is global. • These macro are defined by ` <keyword> or back quote < keywords> Ex ‘ timescale 1ns/1ns ` define DATA_WIDTH 8 `include `ifdefined • These can be defined inside module as well outside module except `timescale which is always defined outside the main module
• 72.
  Timescale • To definethe simulation time unit we need a reference time unit. • `timescale is used for specifying the reference time unit for the simulator. • This time unit we can define at the top of the module or outside module. • `timescale <reference_time_unit>/<time_precision> • The default timescale depends on vender to vender. • The default timescale for cadence is 1ns/1ns. `timescale 1ns/1ns Time precision Time Unit
• 73.
  Timescale • `timescale time_unit/ precision • Time Unit: this is the basic simulation time unit. • This time unit is responsible for all the signal to pass the data at the given time multiplied by the time unit. • Precision: this is the minimum value up to which the precision can be measured. • Precisions represents the minimum delay which needs to be considered during simulation. • It decides that how many decimal point would be used with the time unit. • Range of Timescale • The range for time unit can be from seconds to • ms(mili-second), us(micro-second), ns(nano-second), ps(pico-second) and fs(femto-second).
• 74.
  Timescale • `timescale 1ns/1ns •1ns = 1ns • #1; // = 1ns delay • `timescale 1ns/1ps • #1.003; // = will be considered as a valid delay • #1.0009; // = will be taken as 1 ns only since it is out of the precision value.
• 75.
  Continues to verilog 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Lexical Conventions 7. Verilog data types 8. Abstraction 9. Gate level Abstraction 10. Data flow level Abstraction 11. Behavioral level Abstraction 12. Switch level Abstraction 13. Advance verilog Keywords
• 76.
  Abstraction • Gate level •Data flow Level • Behavioral Level • Switch level Input outpu t Q=dD=in
• 77.
  Continues to verilog 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Lexical Conventions 7. Verilog data types 8. Abstraction 9. Gate level Abstraction 10. Data flow level Abstraction 11. Behavioral level Abstraction 12. Switch level Abstraction 13. Advance verilog Keywords
• 78.
  Gate level Abstraction •This is also known as structural level Abstraction. • In this level the Design is described in terms of gates. • It is very easy to design any circuit in verilog if we have the structure. • For large circuit its difficult to implement in gate level.
• 79.
  Basic gate primitivein verilog AND NAN D OR XOR XNO R BUF NOR NOT Instantiation of gates input wire a, b ; output wire y; and a1 ( y , a, b); nand n1 ( y , a, b); or o1 ( y , a, b); nor no1 ( y , a, b); xor x1 ( y , a, b); xnor xn1 ( y , a, b); buf b1 ( out,in); not n1 (out,in);
• 80.
  NAND 0 1X Z 0 1 1 1 1 1 1 0 X X X 1 X X X Z 1 X X X Basic gate primitive in verilog AND A B Y NAN D A B Y AND 0 1 X Z 0 0 0 0 0 1 0 1 X X X 0 X X X Z 0 X X X
• 81.
  Basic gate primitivein verilog OR NOR OR 0 1 X Z 0 0 1 X X 1 1 1 1 1 X X 1 X X Z X 1 X X NOR 0 1 X Z 0 1 0 X X 1 0 0 0 0 X X 0 X X Z X 0 X X
• 82.
  Basic gate primitivein verilog XOR XNO R XOR 0 1 X Z 0 0 1 X X 1 1 0 X X X X X X X Z X X X X XNO R 0 1 X Z 0 1 0 X X 1 0 1 X X X X X X X Z X X X X
• 83.
  Basic gate primitivein verilog BUF NOT Buf in out 0 0 1 1 X X Z X Buf in out 0 1 1 0 X X Z X
• 84.
  Basic gate primitivein verilog • Instantiation of bufif1 & bufif0  bufif1 (out, in, ctrl);  bufif0 ( out, in, ctrl); • Instantiation of notif1 & notif0  notif1 (out, in, ctrl);  notif0 ( out, in, ctrl); Bufif 1 ctrl ctrl Bufif 0 Notif1 ctrl ctrl Notif0
• 85.
  Basic gate primitivein verilog Bufif 1 ctrl Bufif 1 0 1 X Z 0 Z 0 L L 1 Z 1 H H X Z X X X Z Z X X X Bufif 0 0 1 X Z 0 0 Z H H 1 1 Z L L X X Z X X Z X Z X X ctrl Bufif 0 ctrl in ctrl in
• 86.
  Basic gate primitivein verilog Notif1 ctrl Notif1 0 1 X Z 0 Z 1 L L 1 Z 0 H H X Z X X X Z Z X X X notif 0 0 1 X Z 0 1 Z H H 1 0 Z L L X X Z X X Z X Z X X ctrl Notif0 ctrl in ctrl in
• 87.
  Example of verilogDesign using gate level • I/P => A , B • O/P => Sum & carry Half Adder A B Sum Carry A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 • Boolean Function • Sum = A^B • Carry = A.B
• 88.
  Example of verilogDesign using gate level // this is half adder verilog code module half_adder (S, C , A, B ) // module name & port declaration output S; // output port declarations output C; // output port declarations input A; // input port declarations input B; // input port declarations xor x1 ( S, A, B); // instantiation of xor gate and a1 (C, A, B); // instantiation of and gate endmodule
• 89.
  4 to 1(MUX) 4-to-1 MUX Example of verilog Design using gate level // this is 4to1 MUX verilog code module mux4to1 (Y, A, B, C, D, S1,S0 ) // module //declaration output Y; // output port declarations input A, B, C, D; // input port declarations input S0, S1 // input port declarations // instantiation of and gates and a1( Y1 , A, S0’ , S1’) // instance a1 and a2 (Y2, B , S1’ , S0); // instance a2 and a3 (Y3 , C , S1 , S0’); // instance a3 and a4 (Y4 , D , S1 , S0); // instance a1 // instantiation of or gate or o1(Y, Y1, Y2, Y3, Y4); endmodule
• 90.
  Continues to verilog 1.Introduction to VLSI 2. Introduction to Verilog HDL 3. History 4. Design Methodology 5. Verilog Keywords 6. Lexical Conventions 7. Verilog data types 8. Abstraction 9. Gate level Abstraction 10. Data flow level Abstraction 11. Behavioral level Abstraction 12. Switch level Abstraction 13. Advance verilog Keywords
• 91.
  Data flow levelAbstraction • The gate level approach is very well for small scale logic. • With the increasing level of structure its difficult to model any design in terms of gates. • So therefore we move to data flow level. • With the help of Synthesis Tool we can convert data level code to Gate level code. • All the Boolean function can be implemented using data flow level. • Any data flow level can be expressed using continuous assignment. • Expressions, operators, operands.
• 92.
  Continuous Assignment • Acontinuous assignment is the most basic statement in dataflow modeling. • This continuous assignment is used to drive a value onto a net. • This continuous assignment is equivalent to gate after synthesis. • Continuous assignment can be defined by the keyword assign. • Continuous _assign : : = assign {drive_strength} [ delay] list_of_net_assignment; • Drive strength is optional and can be specified in terms of strength level. • Default value for strength level is strong1 & strong0. • Ex :: assign out = in1 | in2;
• 93.
  Continuous Assignment • assignout_net = in1 & in2; • Continuous assignment are always active and can be updated at any time. • The left hand side value is known as output net and it must be net data type . • wire out_net; // explecitly declared the variable as wire • assign out_net = in1 & in2; // the default declaration of any variable is net type • The right hand side statement is divided into two parts operands & operator. • Whenever the value of operands will change it will directly update ssss the output net. • Operands on right hand side can be reg as well wire. • Delay can be specified in term of #time_unit >= #10 • assign sum #10 = a + b; • assign data[15:0] = dataA[15:0 & dataB[15:0];
• 94.
  Implicit Continuous Assignment •wire data; • assign data =A | B; // regular continuous assignment • wire data = A | B ; // implicit continuous assignment • Implicit net declaration: • Assign data = A | B ; // by defult.
• 95.
  Delay Types • Delayis the time value taken by any continuous expression to transfer its right hand sight value to the left hand sight nets. • There are three ways to define delay in continuous statement. • Regular assignment delay. • Implicit assignment delay. • Net declaration delay.
• 96.
  Delay Types • RiseDelay • Fall Delay • Turn-Off Delay • assign #[10,20,30] dout = in1 & in2 • Min/Typ/Max Delay values • assign #[20:20:30] dout = in1 & in2
• 97.
  Delays(cont…) • Regular assignmentdelay: • assign #10 dout = in1 & in2 ; // delay in the continuous assignment • Implicit assignment delay: • wire #10 dout = in1 & in2 ; // effect is same as regular assignment • Net assignment delay: • wire #10 dout ; • assign dout = in1 & in2; // effect is same in all the expression
• 98.
  Expression, Operator, Operands •Expression:: • asssign data = dataA + dataB; assign reg_out <= regA + regB ; assign data_value = in1 & in2; expression operator operands
• 99.
  Operators • Mathematical : •( / ) divide div = A / B; // the division of A by B • ( * ) multiply Mult = A * B; // Multiplication of A & B • ( % ) modulus mod = A %10 //remainder of A div by 10 • ( + ) addition Sum = A + B; // addition A & B • ( - ) subtraction Sub = A - B; // subtraction of A& B • (** )power operator p = A ** 2; // result is A * A
• 100.
  Operators • Logical: • !logical negation If(! Reset) // logical invert of Reset • && logical and If (A && B) //logically A &B both should Active • || logical or If (a || b) // logically either a or b should be active