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Scan insertion

scan-insertion

kumar gavanurmath

Spyglass dft

spyglass-dft

Burst clock controller

burst-clock-controller-179420123

Scan chain operation

scan-chain-operation

Design for Testability 

design-for-testability-65535130

--Gone through training on scan synthesis flow, scan implementation, scan rule violation report generations and corresponding fixes for all violation. 
--Gone through coverage improvement  by different technique. 
--Lockup latch implementation for different clock domain.
--Testpoint analysis implementation and flow.
- Knowledge in fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other advanced DFT models.
- Knowledge in JTAG, MBIST, Scan Insertion, ATPG, Fault Simulation and at-speed testing. 
- Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test and Mentor ...