RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.
A Reconfigurable RISC-V Core for Approximate Computing
This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.
A platform for learning and experimenting with logic circuits
Verilog miniRV/RISC-V style CPU course project featuring single-cycle and five-stage pipeline designs with hazard handling.
A collection of PDF documents related to the console. Mainly specifications and guides.
Project implementations for the NAND2Tetris (Elements of Computing Systems) course, building a complete computer system from NAND gates to a functional CPU using HDL and low-level system design.
Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground
Computer Architecture UIUC SP 2018
HyperSquid3: a near cycle-accurate Hitachi SH7709S (SH3) core
Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme
Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor
Graphics Processing Unit (GPU) Logisim component (JAR library). It can do blits, sprites, lines, polygons, and text faster than any other currently existing simulated Logisim GPU.
SAP-1 Like CPU / Computer Simulator in HTML and Javascript.
In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.
These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.
A Turing-complete 8-bit computer built entirely on breadboards using discrete logic chips
Aggreage of my past CPU designs.
Turing-Complete 8-bit CPU from 12K+ Logic Gates: Asymmetric 10-bit Addressing & 16-Level Call Stack with Full Toolchain – Solo Built by a 12-Year-Old in 12 days
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