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bus-functional-model

Here are 3 public repositories matching this topic...

chiselverify / chiselverify

A dynamic verification library for Chisel.

testing coverage scala verification chisel constrained-random-verification functional-coverage bus-functional-model chisel-test timed-assertions

Updated Nov 9, 2024
Scala

sjo99-kr / DDR-Multi-Channel-Memory-Controller

Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench

system-verilog memory-controller bus-functional-model uvm-verification

Updated Aug 15, 2026
Verilog

akaeba / eSpiMasterBfm

Bus functional model of an Enhanced Serial Peripheral Interface (eSPI) master

master vhdl intel testbench vhdl93 bfm vhdl-code espi bus-functional-model enhanced-spi

Updated Jun 21, 2025
VHDL

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