#
axi-lite
Here are 54 public repositories matching this topic...
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench
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May 23, 2026 - SystemVerilog
Designing means to communicate as an SPI master, being a part of AXI interface
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Sep 14, 2023 - Verilog
Registers bank with Axi-Lite interface
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Oct 22, 2022 - VHDL
🏄 Custom IP for vector operations
zynq vector vhdl vivado hardware-designs hdl custom-ip fpga-accelerator axi vitis axi-lite vector-operation vector-ops vector-operations
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Aug 31, 2024 - VHDL
UVM Verification of AXI-Lite Sram Controller
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May 24, 2026 - SystemVerilog
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
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Feb 20, 2023 - C
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped
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Nov 21, 2023 - TeX
Прототипирование нейронной сети для распознавания рукописных цифр MNIST на FPGA (плата ZYBO-Z7 с PYNQ). Реализация однослойного персептрона на SystemVerilog с AXI-Lite интерфейсом, интеграция в Vivado и тестирование через Jupyter.
fpga neural-network mnist-classification systemverilog pynq zynq-7000 zybo-z7 edge-ai hardware-accelerator axi-lite on-chip-memory
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Jun 8, 2026 - SystemVerilog
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls
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Dec 3, 2023 - C
EEG-based sleep apnea detection using 1D-CNN trained in MATLAB, implemented in Verilog on Xilinx Zynq-7000 FPGA - Final Year B.E. Project, CEG Anna University 2025
fpga deep-learning matlab eeg verilog vlsi ece biomedical final-year-project edge-computing zynq-7000 1d-cnn axi-lite healthcare-ai sleep-apnea
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Jul 18, 2026
A collection of FPGA-oriented AI accelerator RTL designs, including an 8x8 weight-stationary systolic array and a parameterized event-driven SNN/LIF accelerator, targeting the AMD Kria KV260.
fpga verilog xilinx spiking-neural-networks vivado systemverilog fixed-point verilog-hdl snn axi-stream systemverilog-simulation vivado-simulator axi-lite systemverilog-test-bench systolic-array kria-kv260
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Sep 6, 2026 - SystemVerilog
A FIR filter for 16-bit stereo PCM audio DSP implemented on an FPGA with fixed-point representation.
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Sep 2, 2026 - Verilog
an RTL circuit that sorts the integer values in a momory unit connected with (almost) AXI-Lite
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Jul 19, 2023 - Verilog
RTL implementation of a configurable single-stage DWT and IDWT accelerator with AXI4-Stream, AXI4-Lite coefficient reconfiguration, fixed-point Q15 processing, and support for software-controlled multi-level wavelet decomposition on FPGA.
verilog vivado systemverilog dwt wavelet wavelet-transform axi-stream systemverilog-simulation vivado-simulator idwt axi-lite discrete-wavelet-transform qmf systemverilog-test-bench symlets verilog-hd
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Sep 2, 2026 - Verilog
IEEE-1588 PTP hardware timestamping + latency-measurement unit: DDS clock core, handshake CDC, log2 histogram over AXI-Lite, Simulink PI servo with bit-exact RTL diff
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Sep 16, 2026 - SystemVerilog
A deterministic, fixed-latency tanh non-linear distortion DSP block implemented in Verilog and integrated with AXI-Stream, published as a reference RTL design.
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Sep 10, 2026 - Verilog
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