SimoneDeidier / RL-PROJECT-2023 Star 2 Code Issues Pull requests Final project of Logical Networks course - Politecnico di Milano 2022/23 fsm hardware vhdl finite-state-machine xilinx vivado datapath digital-logic logic-gates testbench digital-design rtl-design hardware-design logic-networks memory-interface Updated Apr 8, 2026 VHDL
scwpark / MQM-Wave-based-Computing-ALU-and-Data-Transfer Star 0 Code Issues Pull requests MQM Wave-based computing/ALU (CPU/GPU/NPU) and Data Transfer Systems for Optics and HBM(Prior Art, 2026.03.04) pam signal-processing hbm ofdm memory-bandwidth data-transmission multi-carrier frequency-encoding parallel-transmission frequency-multiplexing memory-interface multi-bit-modulation multilevel-signal voltage-based-modulation superposition-coding high-speed-link die-to-die-communication nextgenalu wave-based-alu wave-based-computing Updated Apr 23, 2026
Francesco-Barillari / Differential-Filter-on-Memory-VHDL- Star 0 Code Issues Pull requests VHDL implementation of a memory-mapped differential filter controlled by an FSM. vhdl finite-state-machine hardware-design memory-interface Updated Dec 31, 2025 VHDL