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clock-domain-crossing
Here are 45 public repositories matching this topic...
FIFO implementation with different clock domains for read and write.
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Aug 17, 2021 - Verilog
Asynchronous FIFO for transferring data between two asynchronous clock domains
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Jun 3, 2016 - Verilog
Final project for the class "Application Specific Integrated Circuit Development"
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Oct 21, 2021 - SystemVerilog
Utilities for clock-domain crossing with an FPGA
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Jun 27, 2020 - SystemVerilog
In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.
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Nov 20, 2020 - VHDL
A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs
fpga communication-protocol asynchronous embedded-systems fault-tolerant fault-detection network-on-chip interchip-bridge clock-domain-crossing
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Oct 30, 2017 - VHDL
AXI4-Stream Chip-to-Chip Bridge in SystemVerilog featuring Clock Domain Crossing (Async FIFO), Hardware CRC, and full UVM Verification.
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May 29, 2026 - SystemVerilog
Dual-clock asynchronous FIFO in Verilog using Gray-coded CDC pointers, dual-port memory, full/empty flag logic, and a self-checking verification testbench.
fpga eda rtl verilog hardware-designs fifo cdc vlsi digital-design digital-systems asy clock-domain-crossing
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Feb 1, 2026 - Verilog
Dual-clock asynchronous FIFO in Verilog. Gray-coded pointer crossing with two-flop synchronisers, verified with SVA and functional coverage, synthesised in Vivado, and validated on a PYNQ-Z2: 286M words, zero errors.
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Aug 17, 2026 - Verilog
Nexys Video FPGA sensor-fusion HUD integrating Pcam 5C camera input, sonar acquisition, CDC-safe telemetry snapshots, HDMI compositing, OLED telemetry, and debug outputs.
fpga video-processing verilog xilinx sonar vivado hdmi sensor-fusion pwm digilent ov5640 clock-domain-crossing nexys-video artix-7 maxsonar pcam occupancy-grid mipi-csi2 marine-electronics pcam-5c
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Jul 4, 2026 - Verilog
Formally verified vendor-neutral PCIe Gen5 / CXL Type-3 memory-expansion datapath. Unbounded k-induction safety proofs, two-clock CDC, and mutation-checked non-vacuity.
rtl systemverilog computer-architecture formal-verification pcie clock-domain-crossing hardware-verification design-verification symbiyosys cxl
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Aug 2, 2026 - SystemVerilog
Parameterisable dual-clock FIFO in SystemVerilog: Gray-pointer CDC, bound SVA, 8-config self-checking regression (xsim + Icarus), and the Vivado CDC constraints. Placed and routed on ZCU104.
asic fpga verification vivado systemverilog fifo cdc clock-domain-crossing rtl-design systemverilog-assertions
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Jul 28, 2026 - SystemVerilog
Parameterized Synchronous and Asynchronous FIFO implementations in Verilog HDL with Gray-code pointer synchronization, CDC handling, and Vivado verification.
verilog fifo cdc vlsi verilog-hdl digital-design xilinx-vivado gray-code clock-domain-crossing asynchronous-fifo rtl-design synchronous-fifo
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Jul 29, 2026 - Verilog
Gray-pointer asynchronous FIFO with two-flop synchronisers, verified against unrelated clocks and a behavioural metastability model that the binary-pointer version fails.
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Aug 26, 2026 - Python
A basic SPI Slave implementation for Artix-7 FPGA (Basys 3) driven by an ESP32. Features a custom ALU with MAC support and proper CDC synchronization
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Mar 5, 2026 - SystemVerilog
Full-stack Verilog HDL portfolio: gate-level datapaths → UART, CRC-5, Block RAM, DCM clock crossing, and a synthesized 32×32 matrix co-processor on Xilinx FPGA.
fsm fpga rtl matrix-multiplication verilog crc xilinx uart fifo dcm hamming-code digital-design clock-domain-crossing block-ram hardware-design
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Jun 7, 2026 - Verilog
Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and parameterized design. Essential for SoC inter-module communication and multi-clock systems.
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Dec 5, 2025 - Verilog
Parameterizable Asynchronous FIFO with Gray Code Synchronization - A robust clock domain crossing solution in SystemVerilog
asic fpga verilog systemverilog fifo digital-design gray-code clock-domain-crossing asynchronous-fifo rtl-design
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Nov 20, 2025 - SystemVerilog
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