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ultraembedded / core_jpeg

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High throughput JPEG decoder in Verilog for FPGA

fpga mjpeg verilog motion-jpeg verilog-hdl jpeg-decoder axi-stream

Updated Mar 5, 2022
Verilog

KastnerRG / cgra4ml

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An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

asic ai fpga neural-network cnn dnn verilog systemverilog axi-stream asic-design hls4ml

Updated Sep 6, 2026
SystemVerilog

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

fpga udp verilog axi-stream

Updated Mar 15, 2022
Verilog

fcayci / vhdl-axis-uart

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UART to AXI Stream interface written in VHDL

fpga vhdl uart axi-stream

Updated Oct 20, 2022
VHDL

DOUDIU / AXIS-AXI4-AXIS

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This project is designed to delay the output of the video stream in AXI-STREAM format.

fpga ddr axi-stream axi-full

Updated Jul 14, 2024
Verilog

catarinaacsilva / vivado-xilinx-tutorials

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Tutorials or projects example to use Vivado 2019.2 and Vitis

fpga hardware timer software rtos axi-dma memory-mapped axi-stream

Updated Oct 27, 2020
VHDL

shashankov / ReCONNECT

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ReCONNECT: FPGA Optimized RTL-Native Parameterized Network-on-Chip

generator fpga system-verilog noc network-on-chip axi-stream

Updated Aug 12, 2026
SystemVerilog

Yong12315 / FPGA-Engineering-Notes

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Engineering notes and reproducible FPGA examples from real-world development, including RTL design, simulation, verification and debugging.

fpga zynq matlab rtl verilog chinese xilinx vivado digital-signal-processing rapidio engineering-notes axi-stream timing-analysis fpga-tutorial

Updated Aug 26, 2026
Verilog

Lamagraph / pci-ddr-gowin-tangmega138kpro

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Gowin tangmega138k Pro pci+ddr demo

fpga driver pcie axi-stream ddr3 axi4 gowin gowin-fpga ddr-demo tangmega138k-pro pci-demo

Updated Sep 8, 2026
Verilog

ShoukathAli23 / Image-Video-Processing-on-FPGA

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Various video processing projects will be shared here

fpga vhdl image-processing video-processing pynq-z1 axi-stream

Updated May 26, 2020
Jupyter Notebook

IEEEYorkU / lascon-ip

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LASCON — A synthesizable SystemVerilog implementation of the NIST SP 800-232 Ascon lightweight cryptographic standard. Supports AEAD128, Hash256, XOF128, and CXOF128.

nist cryptography fpga systemverilog axi-stream lightweight-cryptography hardware-accelerator