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Fixes for flashing G0/G4 devices - #1506

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Fixes for flashing G0/G4 devices#1506
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fix/g0_g4

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@Nightwalker-87

@Nightwalker-87 Nightwalker-87 commented Aug 10, 2026

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  • Unified similar handling for G0 & G4 series
  • Erase handling for G0 dual bank devices (BKER)
  • Added missing CR flag clearing (PGSERR-Errata)
  • Removed flash erasure delays for G0 (for testing purposes)

(Closes #1473) (Closes #1491)

@Nightwalker-87 Nightwalker-87 added this to the v1.8.1 milestone Aug 10, 2026
@Nightwalker-87 Nightwalker-87 self-assigned this Aug 10, 2026
@Nightwalker-87 Nightwalker-87 moved this to In review in Release v1.8.1 Aug 10, 2026
@Nightwalker-87
Fixes for flashing G0/G4 devices
06dec6c 
- Unified similar handling for G0 & G4 series
- Erase handling for G0 dual bank devices (BKER)
- Added missing CR flag clearing (PGSERR-Errata)
- Removed flash erasure delays for G0 (for testing purposes)
@Nightwalker-87

Nightwalker-87 commented Aug 15, 2026

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@klonyyy Can you have a look at this as well with your device?

@Nightwalker-87

Nightwalker-87 commented Aug 15, 2026 •
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Note on G4 dual-bank detection

Unlike G0's dual-bank variants (G0B1/G0C1/G0B0), where dual-bank is a fixed hardware property correctly reflected in chip_flags (CHIP_F_HAS_DUAL_BANK), G4 Cat.3/Cat.4 devices have a runtime-configurable dual-bank mode via the DBANK bit in FLASH_OPTR (RM0440 sec. 3.7.1). Single-bank is the common default when the option byte was never explicitly set (e.g. via STM32CubeMX/HAL).

Relying on chip_flags alone for the BKER decision would set BKER for any G474/G4 Cat.3 device with >128K flash and an address past the halfway point, regardless of its actual bank configuration — silently targeting the wrong bank on single-bank-configured devices. Thus we may need:

static bool stlink_gx_dual_bank_enabled(stlink_t *sl, bool is_g4) {
  if(!is_g4) {
    // G0 dual-bank variants (G0B1/G0C1/G0B0) are hardware-fixed dual-bank,
    // no runtime option bit — static chip_flags is correct here.
    return (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) != 0;
  }
  // G4 Cat.3/Cat.4: dual-bank is runtime-configurable via DBANK option byte
  // (RM0440 sec 3.7.1). chip_flags alone is not sufficient.
  uint32_t optr = 0;
  stlink_read_debug32(sl, STM32_FLASH_Gx_OPTR, &optr);
  return (optr & (1 << STM32_FLASH_G4_OPTR_DBANK)) != 0;
}

and


bool dual_bank = stlink_gx_dual_bank_enabled(sl, is_g4);

if(dual_bank &&
    ((flashaddr - STM32_FLASH_BASE) >= sl->flash_size / 2)) {
  val |= (1 << bker_bit);
} else {
  val &= ~(1 << bker_bit);
}

@Nightwalker-87
Nightwalker-87 requested a review from klonyyy August 15, 2026 20:50
@klonyyy

klonyyy commented Aug 16, 2026 •
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I tried compiling but I get errors that are already solved by the fix/win_binaries branch. Merged the fix/win_binaries branch into it locally and was able to flash on my STM32G474CC with DBANK checked and unchekced - note that I only have the G4, not G0 unfortunately :/

PS C:\Users\klonyyy\PROJECTS\3rd party\stlink\stlink\build\bin> .\st-flash.exe write D:/test.bin 0x8000000
st-flash 1.8.0-223-gcc3749f
libusb: warning [enumerate_hcd_root_hub] could not infer VID/PID of HCD from 'ROOT\USB\0000'
2026-08-16T12:06:11 INFO common_legacy.c: STM32G47x_G48x: 128 KiB SRAM, 256 KiB flash in at least 2 KiB pages.
file D:/test.bin md5 checksum: 125ca66d4f233c2b6fb99563ecdebb2c, stlink checksum: 0x002b068d
2026-08-16T12:06:11 INFO common_flash.c: Attempting to write 25892 (0x6524) bytes to stm32 address: 134217728 (0x8000000)
-> Flash page at 0x8000000 erased (size: 0x800)
-> Flash page at 0x8000800 erased (size: 0x800)
-> Flash page at 0x8001000 erased (size: 0x800)
-> Flash page at 0x8001800 erased (size: 0x800)
-> Flash page at 0x8002000 erased (size: 0x800)
-> Flash page at 0x8002800 erased (size: 0x800)
-> Flash page at 0x8003000 erased (size: 0x800)
-> Flash page at 0x8003800 erased (size: 0x800)
-> Flash page at 0x8004000 erased (size: 0x800)
-> Flash page at 0x8004800 erased (size: 0x800)
-> Flash page at 0x8005000 erased (size: 0x800)
-> Flash page at 0x8005800 erased (size: 0x800)
-> Flash page at 0x8006000 erased (size: 0x800)

2026-08-16T12:06:11 INFO flash_loader.c: Starting Flash write for WB/WL/G0/G4/L5/U5/C0/C5
  1/12  pages written
  2/12  pages written
  3/12  pages written
  4/12  pages written
  5/12  pages written
  6/12  pages written
  7/12  pages written
  8/12  pages written
  9/12  pages written
 10/12  pages written
 11/12  pages written
 12/12  pages written

2026-08-16T12:06:14 INFO common_flash.c: Starting verification of write complete
2026-08-16T12:06:14 INFO common_flash.c: Flash written and verified! jolly good!
2026-08-16T12:06:14 INFO common_legacy.c: Go to Thumb mode

@Nightwalker-87

Nightwalker-87 commented Aug 16, 2026

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@klonyyy: Yes, the compile errors you initially ran into, do not surprise me. Your intention to merge in the fix/win_binaries branch locally was absolutely the correct approach. I am aware of that you only have a G4 device, but wanted to make sure not to accidentally introduce any regressions there with these changes. Your feedback supports the assumption that this is not the case at least for what is obvious.

@Nightwalker-87

Nightwalker-87 commented Aug 16, 2026 •
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@OpusElectronics, @massimoGG, @rafaelmartins: Can you give it a try at this point?

@Nightwalker-87

Nightwalker-87 commented Aug 28, 2026

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We are still waiting for feedback here.

@massimoGG

massimoGG commented Aug 28, 2026

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Apologies, I will test it this monday.

@massimoGG

massimoGG commented Aug 31, 2026

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I'm still having the same error when flashing to the first bank.

st-flash 1.8.0-218-g06dec6c 
2026-08-31T12:17:20 DEBUG common_legacy.c: *** looking up stlink version *** 
2026-08-31T12:17:20 DEBUG common_legacy.c: st vid = 0x0483 (expect 0x0483) 
2026-08-31T12:17:20 DEBUG common_legacy.c: stlink pid = 0x3748 
2026-08-31T12:17:20 DEBUG common_legacy.c: stlink version = 0x2 
2026-08-31T12:17:20 DEBUG common_legacy.c: jtag version = 0x2e 
2026-08-31T12:17:20 DEBUG common_legacy.c: swim version = 0x7 
2026-08-31T12:17:20 DEBUG common_legacy.c: stlink current mode: mass 
2026-08-31T12:17:20 DEBUG usb.c: JTAG/SWD freq set to 0 
2026-08-31T12:17:20 DEBUG common_legacy.c: stlink current mode: mass 
2026-08-31T12:17:20 DEBUG common_legacy.c: *** stlink_enter_swd_mode *** 
2026-08-31T12:17:20 DEBUG common_legacy.c: Loading device parameters.... 
2026-08-31T12:17:20 DEBUG common_legacy.c: *** stlink_core_id *** 
2026-08-31T12:17:20 DEBUG common_legacy.c: core_id = 0x0bc11477 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x410cc601 at 0xe000ed00 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x410cc601 at 0xe000ed00 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x10016467 at 0x40015800 
2026-08-31T12:17:20 DEBUG chipid.c: detected chip_id parameters 

2026-08-31T12:17:20 DEBUG chipid.c: # Device Type: STM32G0Bx_G0Cx 
2026-08-31T12:17:20 DEBUG chipid.c: # Reference Manual: RM0444 // also RM454 
2026-08-31T12:17:20 DEBUG chipid.c: # 
2026-08-31T12:17:20 DEBUG chipid.c: chip_id 0x467 
2026-08-31T12:17:20 DEBUG chipid.c: flash_type 6 
2026-08-31T12:17:20 DEBUG chipid.c: flash_size_reg 0x1fff75e0 
2026-08-31T12:17:20 DEBUG chipid.c: flash_pagesize 0x800 
2026-08-31T12:17:20 DEBUG chipid.c: sram_size 0x24000 
2026-08-31T12:17:20 DEBUG chipid.c: bootrom_base 0x1fff0000 
2026-08-31T12:17:20 DEBUG chipid.c: bootrom_size 0x7000 
2026-08-31T12:17:20 DEBUG chipid.c: option_base 0x1fff7800 
2026-08-31T12:17:20 DEBUG chipid.c: option_size 0x80 
2026-08-31T12:17:20 DEBUG chipid.c: flags 13 

2026-08-31T12:17:20 DEBUG chipid.c: otp_base 0 

2026-08-31T12:17:20 DEBUG chipid.c: otp_size 0 

2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0xffff0200 at 0x1fff75e0 
2026-08-31T12:17:20 INFO common_legacy.c: STM32G0Bx_G0Cx: 144 KiB SRAM, 512 KiB flash in at least 2 KiB pages. 
2026-08-31T12:17:20 DEBUG common_legacy.c: *** stlink_force_debug_mode *** 
2026-08-31T12:17:20 WARN common_flash.c: Flash base use default L0 address 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0000000000 at 0x40015808 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0x00001800 to 0x40015808 
2026-08-31T12:17:20 DEBUG common_legacy.c: *** stlink_status *** 
2026-08-31T12:17:20 DEBUG usb.c: core status: 03030003 
2026-08-31T12:17:20 DEBUG common_legacy.c: core status: halted 
file bootloader.bin md5 checksum: 6f8603cb92af701a91d2f11e84dae, stlink checksum: 0x0005a09f 
2026-08-31T12:17:20 INFO common_flash.c: Attempting to write 4452 (0x1164) bytes to stm32 address: 134479872 (0x8040000) 
2026-08-31T12:17:20 DEBUG common_legacy.c: *** stlink_core_id *** 
2026-08-31T12:17:20 DEBUG common_legacy.c: core_id = 0x0bc11477 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0000000000 at 0x40022010 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0x000003fa to 0x40022010 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0xc0000000 at 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0x45670123 to 0x40022008 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0xcdef89ab to 0x40022008 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x40000000 at 0x40022014 
2026-08-31T12:17:20 DEBUG common_flash.c: Successfully unlocked flash 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x40000000 at 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0x40000002 to 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x40000002 at 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0x40002002 to 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x40002002 at 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0x40012002 to 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x00060000 at 0x40022010 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x40012002 at 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0x40012000 to 0x40022014 
2026-08-31T12:17:20 DEBUG usb.c: WRITEDEBUGREG wait error (0x14), delaying 1000 us and retry 
2026-08-31T12:17:20 DEBUG usb.c: WRITEDEBUGREG wait error (0x10), delaying 2000 us and retry 
2026-08-31T12:17:20 DEBUG usb.c: WRITEDEBUGREG wait error (0x10), delaying 4000 us and retry 
2026-08-31T12:17:20 DEBUG usb.c: WRITEDEBUGREG wait error (0x10) 
2026-08-31T12:17:20 DEBUG usb.c: READDEBUGREG wait error (0x10), delaying 1000 us and retry 
2026-08-31T12:17:20 DEBUG usb.c: READDEBUGREG wait error (0x10), delaying 2000 us and retry 
2026-08-31T12:17:20 DEBUG usb.c: READDEBUGREG wait error (0x10), delaying 4000 us and retry 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x40002000 at 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0xc0002000 to 0x40022014 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x00000080 at 0x40022010 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0x00000080 at 0x40022010 
2026-08-31T12:17:20 ERROR common_flash.c: Flash programming error: 0x00000080 
2026-08-31T12:17:20 WARN common_flash.c: Failed to erase_flash_page(0x8040000) == -1 
2026-08-31T12:17:20 ERROR common_flash.c: Failed to erase the flash prior to writing 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0xffffffff at 0x08040004 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_reg 
2026-08-31T12:17:20 DEBUG common_legacy.c: *** stlink_run *** 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_reg 
2026-08-31T12:17:20 DEBUG read_write.c: (16) *** 
2026-08-31T12:17:20 DEBUG common_legacy.c: data_len = 8 0x8 
 80 00 13 60 00 00 00 41 
2026-08-31T12:17:20 DEBUG usb.c: r_idx (16) = 0x41000000 
stlink_fwrite_flash() == -1 
2026-08-31T12:17:20 DEBUG common_legacy.c: *** stlink_exit_debug_mode *** 
2026-08-31T12:17:20 DEBUG common_legacy.c: stlink current mode: debug (jtag or swd) 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_write_debug32 0xa05f0000 to 0xe000edf0 
2026-08-31T12:17:20 DEBUG read_write.c: *** stlink_read_debug32 0000000000 at 0xe000edfc 
2026-08-31T12:17:20 DEBUG common_legacy.c: *** stlink_close ***```

@rafaelmartins

rafaelmartins commented Aug 31, 2026

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I've had a quick look and the fix seems incomplete. I'll give it a shot when I get more time, but I'm currently busy with other stuff.

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@klonyyy klonyyy Awaiting requested review from klonyyy

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@Nightwalker-87 Nightwalker-87

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bug/fixed component/stlink-lib target/stm32g0 target/stm32g4

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Release v1.8.1
Status: In review

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v1.8.1

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Successfully merging this pull request may close these issues.

[STM32G0B0CE]: Flashing always fails on second bank (0x08040000) STM32G0B1RE: st-flash fails seemingly randomly

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@Nightwalker-87 @klonyyy @massimoGG @rafaelmartins