Cortex-M division-by-zero exception changes #992

On Cortex-M, by default, division with a zero divisor results in a zero quotient with no exception raised. This is true for both hardware and Renode.

Cortex-M cores have a Configuration and Control register which contains a flag called DIV_0_TRP, which, when set, causes division with a zero divisor raise a UsageFault.

In previous versions of Renode, the value of this flag was ignored unless the FilterCcrDiv0Write property on the CPU instance was manually set to false. As a consequence, division-by-zero exceptions were not raised even if the software explicitly enabled them.

Starting with commit 2ab85e7, FilterCcrDiv0Write is set to false by default, and division-by-zero exceptions are raised when the DIV_0_TRP flag is set to true. This new behaviour is more accurate to the ARM specification.

Restoring old behaviour

If the old behaviour of ignoring division-by-zero exceptions is desirable, it can be restored by setting the FilterCcrDiv0Write property to true on the relevant cores.

To restore the old behaviour, you can add

cpu FilterCcrDiv0Write True

to your resc files, or

Execute Command          cpu FilterCcrDiv0Write True

to your robot files, where cpu refers to a CPU.CortexM instance.