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1. Router_UVM Router_UVM Public

   Scalable UVM Testbench for a 4-Agent router. Implements Virtual Sequencers, RAL, multi-port Scoreboarding, Functional Coverage, and DPI-C Golden Model.

   SystemVerilog 2

2. axi-apb-bridge-uvm axi-apb-bridge-uvm Public

   I am making this UVM Testbench from scratch so I can practice verifying designs from ETH Zurich's PULP Platform

   SystemVerilog

3. Agentic_AI_Sandbox Agentic_AI_Sandbox Public

   Work-In-Progess. This is a repo for experimental RAG's and Agentic Tools that I'm developing

   Python 1

4. TileAlgorithms TileAlgorithms Public

   I made this Visualizer to demonstrate Convolution and Cross-Correlation Tiled Cache-Access Implementations / Also, I made source code to practice writing the indicing for these problems, and an int…

   C

5. LeetcodeWorkspace LeetcodeWorkspace Public

   This is a collection of some of the leetcode problems I've done.

   Python

6. System_Verilog_Workshop System_Verilog_Workshop Public

   A dumping-ground for things I'm working on/ practicing/learning

   SystemVerilog