Bryan，date:2025.4.21  time:17：20,build.

The Bryan processor adopts a sequential two-stage pipeline structure, namely the instruction fetch (IF) and the integrated stage (ID+EX+MEM+WB) that includes instruction decoding, execution, memory access, and write-back functions. Adopting the Harvard architecture, it separates the instruction access and data memory access paths, and also provides a complete SoC implementation solution, including the ICB bus architecture and common peripherals.