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LogicOR - Digital Logic Simulator

LogicOR is a browser-based digital logic simulator built with React, TypeScript, Zustand, and SVG. It is designed for engineering-focused circuit editing, fast signal feedback, and practical analysis (truth table + Karnaugh export).

Screenshot

LogicOR Workbench

Key Features

  • Engineering-style canvas:
    • Orthogonal (grid-like) wire routing
    • Zoom, pan, and grid snapping
    • Branching and waypoint editing on connections
  • Core digital components:
    • INPUT, OUTPUT (lamp), CLK, TEXT, DISPLAY (0..127)
    • AND, OR, NOT, NAND, NOR, XOR, XNOR
    • DFF, JKFF, TFF, SRFF
  • Advanced components:
    • 8421 -> Gray transcoder
    • MUX 4:1
    • DEMUX 1:4
    • PROGRESS controller (Q1..Q10, active-low outputs)
    • FA1 (1-bit full adder)
  • Analysis and export:
    • Truth table export to CSV
    • Karnaugh maps export to CSV (including FF states and next-state functions)
  • Language support:
    • UI translations: EN, DE, ES, JA
    • Language selector in the app header
    • Automatic language detection from browser settings on first load
  • Persistence:
    • Cookie consent prompt on startup
    • Project/theme/language persistence when consent is granted

Requirements

  • Node.js 20.19+ or 22.12+ (recommended)
  • npm

Quick Start

npm install
npm run dev

Open the local URL shown by Vite (usually http://localhost:5173).

Build for Production

npm run build
npm run preview

Usage Guide

1. Place Components

  • Drag a component from the left palette to the canvas, or click it to place in workspace.
  • Move components by dragging.

2. Connect Signals

  • Start from an output pin and finish on an input pin.
  • Connections are rendered as orthogonal engineering-style wires.
  • Input pins accept one connection per input index.

3. Edit Wires

  • Select a connection and double-click on wire to add a waypoint.
  • Drag waypoint to reshape route.
  • Double-click waypoint to remove it.
  • Shift + click on an existing wire to start a branch from that wire.

4. Simulate

  • Double-click INPUT to toggle 0/1.
  • Double-click CLK to set frequency in Hz (0 stops the clock).
  • Shift + click on CLK toggles clock pass-through mode (IN-OUT).
  • Shift + double-click on OUTPUT toggles pass-through mode.

5. Analyze and Export

  • Go to the Analiza tab in the right sidebar.
  • Export truth table CSV.
  • Export Karnaugh maps CSV (2-4 variables total: inputs + FF states).

6. Change Language

  • Use the language selector in the top app bar.
  • Available languages: English (EN), Deutsch (DE), Español (ES), 日本語 (JA).
  • On first load, the app picks language from browser preferences.
  • If cookies are accepted, the selected language is restored on next visit.

Keyboard and Mouse Shortcuts

  • Esc - cancel wire drawing / clear selection
  • Delete or Backspace - delete selected item
  • Arrow keys - rotate selected component by 90 degrees
  • Shift + drag or middle mouse drag - pan canvas
  • Mouse wheel - zoom
  • Alt + drag - draw free orthogonal helper wire on grid

Component Reference

Basic

  • INPUT - manual logic source (0/1)
  • OUTPUT - lamp indicator driven by input signal
  • CLK - configurable frequency source
  • TEXT - editable label element
  • DISPLAY - 7-bit numeric display (B6..B0, range 0..127)

Advanced Blocks

  • 8421 -> Gray
    • Inputs: B3 B2 B1 B0
    • Outputs: G3 G2 G1 G0
  • MUX 4:1
    • Inputs: X0 X1 X2 X3 S1 S0
    • Output: Y
  • DEMUX 1:4
    • Inputs: X S1 S0
    • Outputs: Y0 Y1 Y2 Y3
  • PROGRESS
    • Inputs: B3 B2 B1 B0
    • Outputs: Q1..Q10 (active-low)
  • FA1 (full adder, 1-bit)
    • Inputs: A B Cin
    • Outputs: S Cout

Project Persistence and Cookie Consent

  • On first load, the app asks for cookie consent.
  • If accepted:
    • Project state is persisted in browser storage
    • Theme mode is persisted (system, light, dark)
    • UI language is persisted (EN, DE, ES, JA)
    • Canvas state is restored on reload
  • If declined:
    • Project/theme/language persistence is disabled and cleared

Troubleshooting

  • Cannot connect to an input pin:
    • The input may already be occupied.
    • Remove the existing connection first.
  • Wires look wrong:
    • Select connection and rebuild route with waypoints.
    • Use grid-aligned movement for clean paths.
  • Karnaugh export disabled:
    • Ensure total variables (inputs + FF states) is between 2 and 4.
    • Ensure at least one OUTPUT or FF exists.
  • Development server warning 431 Request Header Fields Too Large:
    • This project avoids large cookie payloads by using browser storage for project data.
    • Clear old browser cookies for this host if needed.

Technology Stack

  • React 19
  • TypeScript
  • Zustand
  • Vite
  • SVG rendering

License

Educational project. Use freely for learning and experimentation.

Releases

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