[VeriblePreProcessor][3]: Passing macros defined using "+define" to "VerilogPreprocess" class - #1374
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karimtera wants to merge 9 commits into
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[VeriblePreProcessor][3]: Passing macros defined using "+define" to "VerilogPreprocess" class#1374karimtera wants to merge 9 commits into
karimtera wants to merge 9 commits into
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…o generate all variants with the new mode generate-variants
…ass for the moment.
"verible::CmdPositionalArguments" class only supports these types so far: SV files, +define+<name>[=<value>], and +incdir+<dir>.
hzeller
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Aug 15, 2022
hzeller
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Since this contains a lot of the changes of the previous PRs, let's first finish the previous ones to reduce the potential merge headaches.
| // add the macro definition to memeory. | ||
| RegisterMacroDefinition(macro_definition); | ||
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| return absl::OkStatus(); |
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If this only ever returns 'ok status' anyway, let's not bother with error handling for now and just have it a void function.
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Closed as a duplicate of #1424 |
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NOTE: This is a part of the sequentially splitted PRs from PR #1360.
Description:
Adding an interface function
AddDefineFromCmdLineto use the macros added by+define+\<foo>argument toVerilogPreprocess.