[BUG] accepting !<reduction_op> without parentheses should be rejected #2569

Describe the bug

Verible incorrectly accepts the syntax !|v, !&v, and !^v (logical NOT applied directly to a reduction operator expression without parentheses). Per the IEEE 1800-2017 SystemVerilog standard, this is a syntax error because the operand of the unary ! (logical negation) operator must be a primary expression, and an unparenthesized reduction operation like |v is not a primary.

Icarus Verilog, Verilator and ModelSim correctly reject these constructs with a syntax error.
To Reproduce

module minimal;
    reg [3:0] v;
    wire y;

    // BUG: according to IEEE 1800-2017 SystemVerilog standard, !|v, !&v and !^v should be rejected
    //      correct syntax shoule be !(|v)
    assign y = !^v;
    assign y = !|v;
    assign y = !&v;

endmodule

command
verible-verilog-syntax minimal.sv

Actual behavior:

Accepted the invaild code.

Expected behavior

reject it