verible-verilog-format fails to parse a macro appearing alongside named parameter assignments in an instantiation parameter list. A macro as the entire param list parses fine.
$ verible-verilog-format --failsafe_success=false - < repro.sv
-: <stdin>:2:16-29: syntax error at token "`MY_PARAM_INST"
Macro-first also fails (#(MY_PARAM_INST, .W(8))→ syntax error at token "."), and a macro in a port *connection* list fails lexical-equivalence verification.
Works:#(MY_PARAM_INST) alone, and a macro on its own line as a module item.
Version: v0.0-4080-ga0a8d8eb. Since the formatter parses the whole file, one such line makes the entire file unformattable, including --lines ranges elsewhere.
Related: #812 (macro in port declaration), #2289 (macros in delay/always positions).
verible-verilog-format fails to parse a macro appearing alongside named parameter assignments in an instantiation parameter list. A macro as the entire param list parses fine.
Sources: #812, #2289