diff --git a/howto/FlowSender/FlowSender.md b/howto/FlowSender/FlowSender.md
new file mode 100644
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+++ b/howto/FlowSender/FlowSender.md
@@ -0,0 +1,31 @@
+# GPStudio Flow sender 
+
+In this tutorial, we will see how GPSudio can send an image from a host computer to an FPGA,  processes it, then send it back to the PC. This functionality can be very useful when debugging IPs,  and when working with devices with no image sensors.  
+
+
+
+1. First, let's create a simple project with the `gpnode_gui` utility. We will use the `dreamcam_c3` board, and consider only the USB IP.![](/home/kamel/Desktop/1.png)
+
+2. In this example, we will send a `cat.jpg` image though USB , perform a 3x3 convolution on it, send it back through USB, and finally display it on GPStudios' viewer. To do so, connect your blocks in the following way:
+
+   ![](./flow.png)
+
+   - The image will be sent though out0
+   - The in0 viewer will display the original sent image 
+   - The in1 viewer will display the "convolved" image
+
+3. Save, generate, compile and implant you design on the Cyclone III FPGA using the usual commands ...
+
+4. When opening the viewer, you should have something like this:
+
+   ![](./gui.png)
+
+5. Go to the flow sender menu and select the directory where your pictures are stored. Select an image, and resize it to a specific width and hight if needed. In the example, we will use a 180x180 resolution since the image width is a static parameter of the convolution IP.
+
+6. Click on : Send to outX, where X is the flow you connected (out0 in our case), you should expect something like this on the output:
+
+   ![](./result.png)
+
+Don't forget to enable all your processes, and to set the correct image width according to the IP. Moreover, the flow-sender might not work well on the first frames (considering the latency to fill the FIFOs ), you can spam the send flow button to send the frame multiple times.
+
+That's all folks ;)
\ No newline at end of file
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diff --git a/support/process/debayer33/debayer33.vhd b/support/process/debayer33/debayer33.vhd
new file mode 100644
index 00000000..0ce779ba
--- /dev/null
+++ b/support/process/debayer33/debayer33.vhd
@@ -0,0 +1,160 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+use 	ieee.math_real.all;
+
+entity debayer33 is
+generic( 	CLK_PROC_FREQ 	: integer;
+			IM_WIDTH 		: integer := 1280;
+			IM_HEIGHT		: integer := 960;
+			COLOR_CHANNELS	: integer := 3;
+			DATA_SIZE		: integer := 8
+			);
+port(
+		clk_proc			: in std_logic;
+		reset_n				: in std_logic;	
+	
+		------------------------- in flow -----------------------
+		in_data				: in std_logic_vector(DATA_SIZE-1 downto 0);
+		in_fv				: in std_logic;
+		in_dv				: in std_logic;
+		
+		------------------------ out flow -----------------------
+		out_fv				: out std_logic;
+		out_dv				: out std_logic; 
+		out_data			: out std_logic_vector((COLOR_CHANNELS*DATA_SIZE)-1 downto 0);
+
+		------------------------- bus_sl ------------------------
+		addr_rel_i          : in std_logic_vector(3 downto 0);
+		wr_i                : in std_logic;
+		rd_i                : in std_logic;
+		datawr_i            : in std_logic_vector(31 downto 0);
+		datard_o            : out std_logic_vector(31 downto 0);
+		
+		------------------------- for sim -------------------------
+		sim_en				: in std_logic;
+		bayer_code_sim		: in std_logic_vector(1 downto 0);
+		test_count_x_out	: out std_logic_vector(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
+		test_count_y_out	: out std_logic_vector(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0)	
+		
+	);
+end entity;
+
+
+
+architecture structural of debayer33 is
+
+component debayer33_slave is
+	generic (
+		CLK_PROC_FREQ : integer
+	);
+	port (
+		clk_proc              : in std_logic;
+		reset_n               : in std_logic;
+
+		---------------- dynamic parameters ports ---------------
+		status_reg_enable_bit : out std_logic;
+		bayer_code    		  : out std_logic_vector(1 downto 0);
+
+		--======================= Slaves ========================
+
+		------------------------- bus_sl ------------------------
+		addr_rel_i            : in std_logic_vector(3 downto 0);
+		wr_i                  : in std_logic;
+		rd_i                  : in std_logic;
+		datawr_i              : in std_logic_vector(31 downto 0);
+		datard_o              : out std_logic_vector(31 downto 0)
+	);
+end component;
+
+component debayer33_process is
+generic( 	CLK_PROC_FREQ 	: integer;
+			IM_WIDTH 		: integer := 1280;
+			IM_HEIGHT		: integer := 960;
+			COLOR_CHANNELS	: integer := 3;
+			DATA_SIZE		: integer := 8
+			);
+port(
+		clk_proc			: in std_logic;
+		reset_n				: in std_logic;	
+		
+		------------------------- from slave -------------------------
+		bayer_code_slave	: in std_logic_vector(1 downto 0);	
+	
+		------------------------- in flow -----------------------
+		in_data				: in std_logic_vector(DATA_SIZE-1 downto 0);
+		in_fv				: in std_logic;
+		in_dv				: in std_logic;
+		
+		------------------------ out flow -----------------------
+		out_data			: out std_logic_vector((COLOR_CHANNELS*DATA_SIZE)-1 downto 0);
+		out_fv				: out std_logic;
+		out_dv				: out std_logic; 
+		
+		------------------------- for sim -------------------------
+		sim_en				: in std_logic;
+		bayer_code_sim		: in std_logic_vector(1 downto 0);
+		test_count_x_out	: out std_logic_vector(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
+		test_count_y_out	: out std_logic_vector(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0)			
+	);
+end component;
+
+signal bayer_code_slave_int : std_logic_vector(1 downto 0);	
+
+begin
+
+u0 : debayer33_slave
+		generic map(
+			CLK_PROC_FREQ 	=> CLK_PROC_FREQ
+		)
+		port map(
+			clk_proc              => clk_proc,
+			reset_n               => reset_n,
+
+			---------------- dynamic parameters ports ---------------
+			status_reg_enable_bit => open,
+			bayer_code    		  => bayer_code_slave_int,
+
+			--======================= Slaves ========================
+
+			------------------------- bus_sl ------------------------
+			addr_rel_i            => addr_rel_i,
+			wr_i                  => wr_i,
+			rd_i                  => rd_i,
+			datawr_i              => datawr_i,
+			datard_o              => datard_o
+		);
+	
+u1 : debayer33_process 
+		generic map(
+			CLK_PROC_FREQ 	=> CLK_PROC_FREQ,
+			IM_WIDTH		=> IM_WIDTH,
+			IM_HEIGHT 		=> IM_HEIGHT,
+			COLOR_CHANNELS	=> COLOR_CHANNELS,
+			DATA_SIZE		=> DATA_SIZE		
+		)
+		port map(
+			clk_proc		=> clk_proc,
+			reset_n			=> reset_n,
+	
+			------------------------- from slave -------------------------
+			bayer_code_slave=> bayer_code_slave_int,
+			
+			------------------------- in flow -----------------------
+			in_data			=> in_data,
+			in_fv			=> in_fv,
+			in_dv			=> in_dv,
+		
+			------------------------ out flow -----------------------
+			out_data		=> out_data,
+			out_fv			=> out_fv,
+			out_dv 			=> out_dv,
+			
+			------------------------- for sim -------------------------
+			sim_en				=> sim_en,
+			bayer_code_sim		=> bayer_code_sim,
+			test_count_x_out	=> test_count_x_out,
+			test_count_y_out	=> test_count_y_out
+		);
+
+end architecture;
\ No newline at end of file
diff --git a/support/process/debayer33/debayer33_process.vhd b/support/process/debayer33/debayer33_process.vhd
new file mode 100644
index 00000000..740c0532
--- /dev/null
+++ b/support/process/debayer33/debayer33_process.vhd
@@ -0,0 +1,408 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+use 	ieee.math_real.all;
+
+
+
+
+entity debayer33_process is
+generic( 	CLK_PROC_FREQ	: integer;
+			IM_WIDTH 		: integer := 1280;
+			IM_HEIGHT		: integer := 960;
+			COLOR_CHANNELS	: integer := 3;
+			DATA_SIZE		: integer := 8
+			);
+port(
+		clk_proc			: in std_logic;
+		reset_n				: in std_logic;
+
+		------------------------- from slave -------------------------
+		bayer_code_slave	: in std_logic_vector(1 downto 0);
+
+		------------------------- in flow -----------------------
+		in_data				: in std_logic_vector(DATA_SIZE-1 downto 0);
+		in_fv				: in std_logic;
+		in_dv				: in std_logic;
+
+		------------------------ out flow -----------------------
+		out_fv				: out std_logic;
+		out_dv				: out std_logic;
+		out_data			: out std_logic_vector((COLOR_CHANNELS*DATA_SIZE)-1 downto 0);
+
+		------------------------- for sim -------------------------
+		sim_en				: in std_logic;
+		bayer_code_sim		: in std_logic_vector(1 downto 0);
+		test_count_x_out	: out std_logic_vector(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
+		test_count_y_out	: out std_logic_vector(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0)
+
+	);
+end entity;
+
+
+
+architecture rtl of debayer33_process is
+
+component div_5 is
+	port
+	(
+		denom		: in std_logic_vector (2 downto 0);
+		numer		: in std_logic_vector (10 downto 0);
+		quotient	: out std_logic_vector (10 downto 0);
+		remain		: out std_logic_vector (2 downto 0)
+	);
+end component;
+
+----------
+signal test_count_x_out_int : unsigned(integer(ceil(log2(real(IM_WIDTH))))-1 downto 0);
+signal test_count_y_out_int : unsigned(integer(ceil(log2(real(IM_HEIGHT))))-1 downto 0);
+type state_count_line_out_enum is(s0,s1);
+signal state_count_line_out	: state_count_line_out_enum;
+
+
+----------
+type state_demosaic_enum is(s0,s1,s2);
+signal state_demosaic : state_demosaic_enum;
+
+type ramshift_array is array(IM_WIDTH-1 downto 0) of std_logic_vector(DATA_SIZE-1 downto 0);
+signal ramshift_0, ramshift_1, ramshift_2 : ramshift_array;
+--type ramshift_2_array is array(2 downto 0) of std_logic_vector(DATA_SIZE-1 downto 0);
+--signal ramshift_2 : ramshift_2_array;
+
+signal bayer_code_int, code_demosaic_int : std_logic_vector(1 downto 0);
+
+signal line_dv_int, enable_debayer_int : std_logic;
+
+
+signal pixel_count_int, line_count_int : unsigned(31 downto 0);
+
+
+signal red_tmp, blue_tmp : unsigned(DATA_SIZE+1 downto 0);
+signal green_tmp : unsigned(DATA_SIZE+2 downto 0);
+
+
+signal enable_debayer_latched_1_int, enable_debayer_latched_2_int, line_dv_tmp : std_logic;
+signal path_1_int, path_2_int : std_logic_vector(1 downto 0);
+signal denom_int, rem_int, threshold_int : std_logic_vector(2 downto 0);
+signal red_tmp_1_latched_int, blue_tmp_1_latched_int : unsigned(DATA_SIZE+1 downto 0);
+signal red_tmp_2_latched_int, blue_tmp_2_latched_int : unsigned(DATA_SIZE-1 downto 0);
+signal green_tmp_1_latched_int, green_out_tmp : unsigned(DATA_SIZE+2 downto 0);
+signal green_tmp_2_latched_int : std_logic_vector(DATA_SIZE+2 downto 0);
+
+begin
+
+
+bayer_code_int <= bayer_code_slave when sim_en = '0' else bayer_code_sim;
+
+
+--test count pour x et y du demosaic
+test_count_x_out 	<= std_logic_vector(test_count_x_out_int);
+test_count_y_out	<= std_logic_vector(test_count_y_out_int);
+process(clk_proc, reset_n)
+begin
+if reset_n = '0' then
+	test_count_x_out_int	<= (others => '0');
+	test_count_y_out_int	<= (others => '0');
+	state_count_line_out	<= s0;
+elsif rising_edge(clk_proc) then
+	if line_dv_tmp = '1' then
+		test_count_x_out_int		<= test_count_x_out_int + 1;
+	else
+		test_count_x_out_int		<= (others => '0');
+	end if;
+
+	case state_count_line_out is
+
+		when s0 =>
+			if in_fv = '1' then
+				if line_dv_tmp = '1' then
+					test_count_y_out_int	<= test_count_y_out_int;
+					state_count_line_out	<= s1;
+				end if;
+			else
+				test_count_y_out_int	<= (others => '0');
+				state_count_line_out	<= s0;
+			end if;
+
+
+		when s1 =>
+			if in_fv = '1' then
+				if line_dv_tmp = '0' then
+					test_count_y_out_int	<= test_count_y_out_int + 1;
+					state_count_line_out	<= s0;
+				end if;
+			else
+				test_count_y_out_int	<= (others => '0');
+				state_count_line_out	<= s0;
+			end if;
+
+		when others => NULL;
+
+	end case;
+
+end if;
+end process;
+
+--on compte les lignes
+process(clk_proc,reset_n)
+begin
+if reset_n = '0' then
+	line_count_int	<= (others => '0');
+	state_demosaic	<= s0;
+elsif rising_edge(clk_proc) then
+	case state_demosaic is
+		when s0 =>--attente
+			if in_fv = '1' then
+				line_count_int	<= line_count_int;
+				if in_dv = '1' then
+					state_demosaic	<= s1;
+				else
+					state_demosaic	<= s0;
+				end if;
+			else
+				line_count_int	<= (others => '0');
+				state_demosaic	<= s0;
+			end if;
+		when s1 =>--attente fin d'image et/ou ligne
+			if in_fv = '1' then
+				if in_dv = '0' then --la ligne vient de se terminer
+					if line_count_int < IM_HEIGHT-1 then--on continue
+						line_count_int	<= line_count_int + 1;
+						state_demosaic	<= s0;
+					else--image
+						line_count_int	<= line_count_int;
+						state_demosaic	<= s2;
+					end if;
+				else
+					line_count_int	<= line_count_int;
+					state_demosaic	<= s1;
+				end if;
+			end if;
+		when s2 => --fin de l'image, on attend que frame valid retombe
+			if in_fv = '0' then
+				line_count_int	<= (others => '0');
+				state_demosaic	<= s0;
+			else
+				line_count_int	<= line_count_int;
+				state_demosaic	<= s2;
+			end if;
+		when others => NULL;
+	end case;
+end if;
+end process;
+
+--pixel pipeline for 3 lines
+--evaluate when debayer should be activated
+process(clk_proc,reset_n)
+begin
+if reset_n = '0' then
+
+	pixel_count_int 	<= (others => '0');
+	enable_debayer_int	<= '0';
+	code_demosaic_int	<= (others => '0');
+	ramshift_0			<= (others => (others => '0'));
+	ramshift_1			<= (others => (others => '0'));
+	ramshift_2			<= (others => (others => '0'));
+
+elsif rising_edge(clk_proc) then
+	if in_fv = '1' then
+		if in_dv = '1' then
+			ramshift_0	<= ramshift_1(0) & ramshift_0(IM_WIDTH-1 downto 1);-- a changer si la taille du kernel change
+			ramshift_1	<= ramshift_2(0) & ramshift_1(IM_WIDTH-1 downto 1);
+			ramshift_2	<= in_data & ramshift_2(IM_WIDTH-1 downto 1);--ramshift_2(2 downto 1);
+		end if;
+	end if;
+
+	if in_fv = '1' then
+		if in_dv = '1' then
+			pixel_count_int <= pixel_count_int + 1;
+		else
+			pixel_count_int	<= (others => '0');
+		end if;
+	else
+		pixel_count_int	<= (others => '0');
+	end if;
+
+	if line_count_int > 1 and line_count_int <= IM_HEIGHT-1 then
+		if pixel_count_int > 1  and pixel_count_int <= IM_WIDTH-1 then
+			enable_debayer_int	<= '1';
+			code_demosaic_int 	<= line_count_int(0) & pixel_count_int(0);
+		else
+			enable_debayer_int	<= '0';
+			code_demosaic_int 	<= (others => '0');
+		end if;
+	else
+		enable_debayer_int 	<= '0';
+		code_demosaic_int 	<= (others => '0');
+	end if;
+
+
+
+end if;
+end process;
+
+
+--debayering
+process(clk_proc, reset_n)
+begin
+if reset_n  = '0' then
+	enable_debayer_latched_1_int	<= '0';
+	path_1_int					<= (others => '0');
+	red_tmp						<= (others => '0');
+	green_tmp					<= (others => '0');
+	blue_tmp					<= (others => '0');
+elsif rising_edge(clk_proc) then
+	if enable_debayer_int = '1' then
+		enable_debayer_latched_1_int	<= '1';
+		path_1_int					<= code_demosaic_int;
+		if code_demosaic_int =  bayer_code_int(1)&bayer_code_int(0) then --"00"
+			red_tmp			<= ("00"&unsigned(ramshift_0(IM_WIDTH-2))) + ("00"&unsigned(ramshift_2(IM_WIDTH-2)));
+			green_tmp 		<= ("000"&unsigned(ramshift_0(IM_WIDTH-1))) + ("000"&unsigned(ramshift_0(IM_WIDTH-3))) + ("000"&unsigned(ramshift_1(IM_WIDTH-2))) + ("000"&unsigned(ramshift_2(IM_WIDTH-1))) + ("000"&unsigned(ramshift_2(IM_WIDTH-3)));
+			blue_tmp 		<= ("00"&unsigned(ramshift_1(IM_WIDTH-1))) + ("00"&unsigned(ramshift_1(IM_WIDTH-3)));
+		elsif code_demosaic_int = bayer_code_int(1)&not(bayer_code_int(0)) then --"01"
+			red_tmp			<= ("00"&unsigned(ramshift_0(IM_WIDTH-1))) + ("00"&unsigned(ramshift_0(IM_WIDTH-3))) + ("00"&unsigned(ramshift_2(IM_WIDTH-1))) + ("00"&unsigned(ramshift_2(IM_WIDTH-3)));
+			green_tmp 		<= ("000"&unsigned(ramshift_0(IM_WIDTH-2))) + ("000"&unsigned(ramshift_1(IM_WIDTH-1))) + ("000"&unsigned(ramshift_1(IM_WIDTH-3))) + ("000"&unsigned(ramshift_2(IM_WIDTH-2)));
+			blue_tmp 		<= ("00"&unsigned(ramshift_1(IM_WIDTH-2)));
+		elsif code_demosaic_int =  not(bayer_code_int(1))& bayer_code_int(0) then --"01" then
+			red_tmp			<= ("00"&unsigned(ramshift_1(IM_WIDTH-2)));
+			green_tmp 		<= ("000"&unsigned(ramshift_0(IM_WIDTH-2))) + ("000"&unsigned(ramshift_1(IM_WIDTH-1))) + ("000"&unsigned(ramshift_1(IM_WIDTH-3))) + ("000"&unsigned(ramshift_2(IM_WIDTH-2)));
+			blue_tmp 		<= ("00"&unsigned(ramshift_0(IM_WIDTH-2))) + ("00"&unsigned(ramshift_1(IM_WIDTH-1))) + ("00"&unsigned(ramshift_1(IM_WIDTH-3))) + ("00"&unsigned(ramshift_2(IM_WIDTH-2)));
+		else
+			red_tmp			<= ("00"&unsigned(ramshift_1(IM_WIDTH-1))) + ("00"&unsigned(ramshift_1(IM_WIDTH-3)));
+			green_tmp 		<= ("000"&unsigned(ramshift_0(IM_WIDTH-1))) + ("000"&unsigned(ramshift_0(IM_WIDTH-3))) + ("000"&unsigned(ramshift_1(IM_WIDTH-2))) + ("000"&unsigned(ramshift_2(IM_WIDTH-1))) + ("000"&unsigned(ramshift_2(IM_WIDTH-3)));
+			blue_tmp 		<= ("00"&unsigned(ramshift_0(IM_WIDTH-2))) + ("00"&unsigned(ramshift_2(IM_WIDTH-2)));
+		end if;
+	else
+		enable_debayer_latched_1_int	<= '0';
+		path_1_int					<= (others => '0');
+		red_tmp						<= (others => '0');
+		green_tmp					<= (others => '0');
+		blue_tmp					<= (others => '0');
+	end if;
+
+
+end if;
+end process;
+
+--process feed divider
+process(clk_proc, reset_n)
+begin
+if reset_n = '0' then
+
+	enable_debayer_latched_2_int	<= '0';
+	path_2_int						<= (others => '0');
+	red_tmp_1_latched_int			<= (others => '0');
+	green_tmp_1_latched_int			<= (others => '0');
+	denom_int						<= "001";
+	blue_tmp_1_latched_int			<= (others => '0');
+
+elsif rising_edge(clk_proc) then
+	if enable_debayer_latched_1_int	= '1' then
+		enable_debayer_latched_2_int	<= '1';
+		path_2_int						<= path_1_int;
+		red_tmp_1_latched_int			<= red_tmp;
+		green_tmp_1_latched_int			<= green_tmp;
+		blue_tmp_1_latched_int			<= blue_tmp;
+		if path_1_int = "00" or path_1_int = "11" then
+			denom_int		<= "101";
+		else
+			denom_int		<= "100";
+		end if;
+	else
+		enable_debayer_latched_2_int	<= '0';
+		path_2_int						<= (others => '0');
+		red_tmp_1_latched_int			<= (others => '0');
+		green_tmp_1_latched_int			<= (others => '0');
+		denom_int						<= (others => '0');
+		blue_tmp_1_latched_int			<= (others => '0');
+	end if;
+end if;
+end process;
+
+
+-- compute pixels
+div_5_inst : div_5 PORT MAP (
+		denom	 => denom_int,-- a changer si la taille du kernel change
+		numer	 => std_logic_vector(green_tmp_1_latched_int),
+		quotient => green_tmp_2_latched_int,
+		remain	 => rem_int
+	);
+
+threshold_int <= "011";
+--cut process
+process(clk_proc, reset_n)
+begin
+if reset_n = '0' then
+
+	red_tmp_2_latched_int		<= (others => '0');
+	green_out_tmp				<= (others => '0');
+	blue_tmp_2_latched_int		<= (others => '0');
+	line_dv_tmp					<= '0';
+
+elsif rising_edge(clk_proc) then
+
+	if enable_debayer_latched_2_int = '1' then
+		line_dv_tmp	<= '1';
+		if path_2_int = "00" then
+			red_tmp_2_latched_int	<= red_tmp_1_latched_int(DATA_SIZE downto 1);
+			blue_tmp_2_latched_int	<= blue_tmp_1_latched_int(DATA_SIZE downto 1);
+			if rem_int > threshold_int then
+				green_out_tmp	<= unsigned(green_tmp_2_latched_int) + "00000000001";
+			else
+				green_out_tmp	<= unsigned(green_tmp_2_latched_int);
+			end if;
+		elsif path_2_int = "01" then
+			red_tmp_2_latched_int	<= red_tmp_1_latched_int(DATA_SIZE+1 downto 2);
+			blue_tmp_2_latched_int	<= blue_tmp_1_latched_int(DATA_SIZE downto 1);
+			green_out_tmp			<= unsigned(green_tmp_2_latched_int);
+		elsif path_2_int = "10" then
+			red_tmp_2_latched_int	<= red_tmp_1_latched_int(DATA_SIZE-1 downto 0);
+			blue_tmp_2_latched_int	<= blue_tmp_1_latched_int(DATA_SIZE+1 downto 2);
+			green_out_tmp			<= unsigned(green_tmp_2_latched_int);
+		else--"11"
+			red_tmp_2_latched_int	<= red_tmp_1_latched_int(DATA_SIZE downto 1);
+			blue_tmp_2_latched_int	<= blue_tmp_1_latched_int(DATA_SIZE downto 1);
+			if rem_int > threshold_int then
+				green_out_tmp	<= unsigned(green_tmp_2_latched_int) + "00000000001";
+			else
+				green_out_tmp	<= unsigned(green_tmp_2_latched_int);
+			end if;
+		end if;
+	else
+		red_tmp_2_latched_int		<= (others => '0');
+		green_out_tmp				<= (others => '0');
+		blue_tmp_2_latched_int		<= (others => '0');
+		line_dv_tmp					<= '0';
+	end if;
+end if;
+end process;
+
+--final process
+process(clk_proc, reset_n)
+begin
+if reset_n = '0' then
+	out_dv 	<= '0';
+	out_data	<= (others => '0');
+elsif rising_edge(clk_proc) then
+	if line_dv_tmp = '1' then
+		out_dv 	<= '1';
+		out_data((COLOR_CHANNELS*DATA_SIZE)-1 downto ((COLOR_CHANNELS-1)*DATA_SIZE)) 		<= std_logic_vector(red_tmp_2_latched_int);
+		out_data(((COLOR_CHANNELS-1)*DATA_SIZE)-1 downto ((COLOR_CHANNELS-2)*DATA_SIZE)) 	<= std_logic_vector(green_out_tmp(DATA_SIZE-1 downto 0));
+		out_data(((COLOR_CHANNELS-2)*DATA_SIZE)-1 downto ((COLOR_CHANNELS-3)*DATA_SIZE)) 	<= std_logic_vector(blue_tmp_2_latched_int);
+		-- red_plane	<= std_logic_vector(red_tmp_2_latched_int);
+		-- green_plane	<= std_logic_vector(green_out_tmp(DATA_SIZE-1 downto 0));
+		-- blue_plane	<= std_logic_vector(blue_tmp_2_latched_int);
+	else
+		out_dv 		<= '0';
+		out_data	<= (others => '0');
+		-- red_plane	<= (others => '0');
+		-- green_plane	<= (others => '0');
+		-- blue_plane	<= (others => '0');
+	end if;
+end if;
+end process;
+
+
+out_fv <= in_fv;
+
+end architecture;
diff --git a/support/process/debayer33/debayer33_slave.vhd b/support/process/debayer33/debayer33_slave.vhd
new file mode 100644
index 00000000..b0112b3f
--- /dev/null
+++ b/support/process/debayer33/debayer33_slave.vhd
@@ -0,0 +1,79 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+library std;
+
+entity debayer33_slave is
+	generic (
+		CLK_PROC_FREQ : integer
+	);
+	port (
+		clk_proc              : in std_logic;
+		reset_n               : in std_logic;
+
+		---------------- dynamic parameters ports ---------------
+		status_reg_enable_bit : out std_logic;
+		bayer_code    		  : out std_logic_vector(1 downto 0);
+
+		--======================= Slaves ========================
+
+		------------------------- bus_sl ------------------------
+		addr_rel_i            : in std_logic_vector(3 downto 0);
+		wr_i                  : in std_logic;
+		rd_i                  : in std_logic;
+		datawr_i              : in std_logic_vector(31 downto 0);
+		datard_o              : out std_logic_vector(31 downto 0)
+	);
+end debayer33_slave;
+
+architecture rtl of debayer33_slave is
+
+	-- Registers address   
+	constant STATUS_REG_REG_ADDR   : natural := 0;
+	constant BAYER_CODE_REG_REG_ADDR : natural := 1;
+
+	-- Internal registers      
+	signal status_reg_enable_bit_reg : std_logic;
+	signal bayer_code_reg    : std_logic_vector (1 downto 0);
+
+begin
+	write_reg : process (clk_proc, reset_n)
+	begin
+		if(reset_n='0') then
+			status_reg_enable_bit_reg <= '0';
+			bayer_code_reg <= (others => '0');
+		elsif(rising_edge(clk_proc)) then
+			if(wr_i='1') then
+				case addr_rel_i is
+					when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
+						status_reg_enable_bit_reg <= datawr_i(0);
+					when std_logic_vector(to_unsigned(BAYER_CODE_REG_REG_ADDR, 4))=>
+						bayer_code_reg <= datawr_i(1) & datawr_i(0);
+					when others=>
+				end case;
+			end if;
+		end if;
+	end process;
+
+	read_reg : process (clk_proc, reset_n)
+	begin
+		if(reset_n='0') then
+			datard_o <= (others => '0');
+		elsif(rising_edge(clk_proc)) then
+			if(rd_i='1') then
+				case addr_rel_i is
+					when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
+						datard_o <= (0 => status_reg_enable_bit_reg, others => '0');
+					when std_logic_vector(to_unsigned(BAYER_CODE_REG_REG_ADDR, 4))=>
+						datard_o <= (1 => bayer_code_reg(1), 0 => bayer_code_reg(0), others => '0');
+					when others=>
+						datard_o <= (others => '0');
+				end case;
+			end if;
+		end if;
+	end process;
+
+	status_reg_enable_bit <= status_reg_enable_bit_reg;
+	bayer_code <= bayer_code_reg;
+
+end rtl;
diff --git a/support/process/debayer33/vsim.wlf b/support/process/debayer33/vsim.wlf
new file mode 100644
index 00000000..8dd417a1
Binary files /dev/null and b/support/process/debayer33/vsim.wlf differ
diff --git a/support/process/sconv/hdl/kernel_3x3.vhd b/support/process/sconv/hdl/kernel_3x3.vhd
index e9802303..4a44838b 100644
--- a/support/process/sconv/hdl/kernel_3x3.vhd
+++ b/support/process/sconv/hdl/kernel_3x3.vhd
@@ -1,124 +1,112 @@
---||================================================================||--
---||-------  VHDL code for a 3x3 kernel image convolution --------- ||--                                                       
---||----------------------------------------------------------------||--
---|| Author	: 	Kamel Eddine ABDELOUAHAB - PhD Student              ||--
---|| Institution :	Institut Pascal - DREAM team                    ||--                                          
---||                Université Blaise Pascal - Clermont Ferrand     ||--                                         
---|| Contact:	abdelouahab.kamel.eddine (at) gmail.com             ||--                                                  
---||================================================================||--
-
+-- Author     : K. Abdelouahab
+-- Company    : DREAM - Institut Pascal - Unviersite Clermont Auvergne
 
 library ieee;
     use ieee.std_logic_1164.all;
     use ieee.numeric_std.all;
     use ieee.math_real.all;
-	
+
 entity kernel_3x3 is
-	generic(
-	PIX_WIDTH		: integer
-	);
-	port (
-	
-		clk_proc,reset_n	:	in	std_logic;
-		in_fv,in_dv			:	in	std_logic;
-		enable_i			:	in	std_logic;
-
-		p11,p12,p13			:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		p21,p22,p23			:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		p31,p32,p33			:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		
-		ker11,ker12,ker13	:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		ker21,ker22,ker23	:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		ker31,ker32,ker33	:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		norm				:	in 	std_logic_vector(PIX_WIDTH-1 downto 0);
-			
-		out_data			:	out	std_logic_vector(PIX_WIDTH-1 downto 0);
-		out_fv,out_dv		:	out	std_logic		
-		);
+    generic(
+        PIX_WIDTH :  integer
+    );
+    port (
+        reset_n           : in  std_logic;
+        clk_proc          : in  std_logic;
+        in_dv             : in  std_logic;
+        in_fv             : in  std_logic;
+        enable_i          : in  std_logic;
+        p11,p12,p13       : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        p21,p22,p23       : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        p31,p32,p33       : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        ker11,ker12,ker13 : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        ker21,ker22,ker23 : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        ker31,ker32,ker33 : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        norm              : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        out_data          : out std_logic_vector(PIX_WIDTH-1 downto 0);
+        out_dv            : out std_logic;
+        out_fv            : out std_logic
+        );
 end kernel_3x3;
 
 
 architecture BHV of kernel_3x3 is
-	
-	signal	p11u,p12u,p13u			:	signed (PIX_WIDTH downto 0);
-	signal	p21u,p22u,p23u			:	signed (PIX_WIDTH downto 0);	
-	signal	p31u,p32u,p33u			:	signed (PIX_WIDTH downto 0);
-	
-	signal	ker11u,ker12u,ker13u	:	signed (PIX_WIDTH downto 0);
-	signal 	ker21u,ker22u,ker23u	:	signed (PIX_WIDTH downto 0);
-	signal	ker31u,ker32u,ker33u	:	signed (PIX_WIDTH downto 0);
-	
-	signal	normi					:	integer range 0 to 8;
-	
-	begin
-	
-	p11u 	<=  signed( '0' & (p11));
-	p12u 	<=  signed( '0' & (p12));
-	p13u 	<=  signed( '0' & (p13));      
-	p21u 	<=  signed( '0' & (p21));
-	p22u 	<=  signed( '0' & (p22));
-	p23u 	<=  signed( '0' & (p23));                                          
-	p31u 	<=  signed( '0' & (p31));
-	p32u 	<=  signed( '0' & (p32));
-	p33u 	<=  signed( '0' & (p33));
-	
-	ker11u 	<=  signed(ker11(ker11'LEFT) & (ker11));
-	ker12u 	<=  signed(ker12(ker12'LEFT) & (ker12));
-	ker13u 	<=  signed(ker13(ker13'LEFT) & (ker13));                                        
-	ker21u 	<=  signed(ker21(ker21'LEFT) & (ker21));
-	ker22u 	<=  signed(ker22(ker22'LEFT) & (ker22));
-	ker23u 	<=  signed(ker23(ker23'LEFT) & (ker23));                                          
-	ker31u 	<=  signed(ker31(ker31'LEFT) & (ker31));
-	ker32u 	<=  signed(ker32(ker32'LEFT) & (ker32));
-	ker33u 	<=  signed(ker33(ker33'LEFT) & (ker33));
-
-	process	(clk_proc)
-	
-		variable	m11	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-		variable	m12	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-		variable	m13	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-		variable	m21	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-		variable	m22	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-		variable	m23	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-		variable	m31	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-		variable	m32	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-		variable	m33	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-  		variable	sum	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-  		variable	res	:	 signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
-  		
-  		
-  	begin
-  	
-  	if (reset_n = '0')	 then
-  			sum :=	(others => '0');
-  	
-  	elsif	(RISING_EDGE(clk_proc)) then  	
-  		if ((in_fv and in_dv and enable_i) = '1') then 
-  			
-  			m11	:=	ker11u * p11u  ;
-  			m12	:=	ker12u * p12u  ;
-  			m13	:=	ker13u * p13u  ;
-  			m21	:=	ker21u * p21u  ;
-  			m22	:=	ker22u * p22u  ;
-  			m23	:=	ker23u * p23u  ;
-  			m31	:=	ker31u * p31u  ;
-  			m32	:=	ker32u * p32u  ;
-  			m33	:=	ker33u * p33u  ;
-  			
-			sum := m11 + m12 + m13 + m21 + m22 + m23 + m31 + m32 + m33;
-					
-			if (sum(sum'left) = '1')	then
-				sum := (others => '0');
-			end if;
-			
-			normi	<=  to_integer (unsigned(norm));
-			res		:=	sum srl normi;
-			out_data <= std_logic_vector (res(PIX_WIDTH -1  downto 0));
-			
-		end if;
-		out_dv	<= in_dv;
-		out_fv	<= in_fv;
-			
-		end if;
-	end process;
-end BHV;	
+
+    signal    p11u,p12u,p13u        : signed (PIX_WIDTH downto 0);
+    signal    p21u,p22u,p23u        : signed (PIX_WIDTH downto 0);
+    signal    p31u,p32u,p33u        : signed (PIX_WIDTH downto 0);
+    signal    ker11u,ker12u,ker13u  : signed (PIX_WIDTH downto 0);
+    signal    ker21u,ker22u,ker23u  : signed (PIX_WIDTH downto 0);
+    signal    ker31u,ker32u,ker33u  : signed (PIX_WIDTH downto 0);
+    signal    normi                 : integer range 0 to 8;
+
+    begin
+
+    p11u     <=  signed( '0' & (p11));
+    p12u     <=  signed( '0' & (p12));
+    p13u     <=  signed( '0' & (p13));
+    p21u     <=  signed( '0' & (p21));
+    p22u     <=  signed( '0' & (p22));
+    p23u     <=  signed( '0' & (p23));
+    p31u     <=  signed( '0' & (p31));
+    p32u     <=  signed( '0' & (p32));
+    p33u     <=  signed( '0' & (p33));
+
+    ker11u     <=  signed(ker11(ker11'LEFT) & (ker11));
+    ker12u     <=  signed(ker12(ker12'LEFT) & (ker12));
+    ker13u     <=  signed(ker13(ker13'LEFT) & (ker13));
+    ker21u     <=  signed(ker21(ker21'LEFT) & (ker21));
+    ker22u     <=  signed(ker22(ker22'LEFT) & (ker22));
+    ker23u     <=  signed(ker23(ker23'LEFT) & (ker23));
+    ker31u     <=  signed(ker31(ker31'LEFT) & (ker31));
+    ker32u     <=  signed(ker32(ker32'LEFT) & (ker32));
+    ker33u     <=  signed(ker33(ker33'LEFT) & (ker33));
+
+    process    (clk_proc)
+
+        variable    m11    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    m12    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    m13    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    m21    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    m22    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    m23    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    m31    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    m32    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    m33    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    sum    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+        variable    res    :     signed (PIX_WIDTH + PIX_WIDTH + 1  downto 0);
+
+    begin
+
+      if (reset_n = '0')     then
+              sum :=    (others => '0');
+
+      elsif    (RISING_EDGE(clk_proc)) then
+          if ((in_fv and in_dv and enable_i) = '1') then
+
+              m11    :=    ker11u * p11u  ;
+              m12    :=    ker12u * p12u  ;
+              m13    :=    ker13u * p13u  ;
+              m21    :=    ker21u * p21u  ;
+              m22    :=    ker22u * p22u  ;
+              m23    :=    ker23u * p23u  ;
+              m31    :=    ker31u * p31u  ;
+              m32    :=    ker32u * p32u  ;
+              m33    :=    ker33u * p33u  ;
+
+              sum := m11 + m12 + m13 + m21 + m22 + m23 + m31 + m32 + m33;
+
+              if (sum(sum'left) = '1')    then
+                  sum := (others => '0');
+              end if;
+
+              normi    <=  to_integer (unsigned(norm));
+              res        :=    sum srl normi;
+              out_data <= std_logic_vector (res(PIX_WIDTH -1  downto 0));
+
+            end if;
+            out_dv    <= in_dv;
+            out_fv    <= in_fv;
+        end if;
+    end process;
+end BHV;
diff --git a/support/process/sconv/hdl/pipline_gen.vhd b/support/process/sconv/hdl/pipline_gen.vhd
index c4f04063..5b9efae4 100644
--- a/support/process/sconv/hdl/pipline_gen.vhd
+++ b/support/process/sconv/hdl/pipline_gen.vhd
@@ -1,54 +1,49 @@
---||================================================================||--
---||-------  VHDL code for a 3x3 kernel image convolution --------- ||--                                                       
---||                File : a generic shift register					||-- 
---||----------------------------------------------------------------||--
---|| Author	: 	Kamel Eddine ABDELOUAHAB - PhD Student              ||--
---|| Institution :	Institut Pascal - DREAM team                    ||--                                          
---||                Université Blaise Pascal - Clermont Ferrand     ||--                                         
---|| Contact:	abdelouahab.kamel.eddine (at) gmail.com             ||--                                                  
---||================================================================||--
-library IEEE;
-use IEEE.std_logic_1164.all;
+-- Author     : K. Abdelouahab
+-- Company    : DREAM - Institut Pascal - Unviersite Clermont Auvergne
+
+library ieee;
+use ieee.std_logic_1164.all;
 
 entity pipline_gen  is
-	generic (
-	PIPLINE_LENGHT	:	integer;
-	WORD_SIZE	:	integer
-	);
-	
-	port (
-	clk_proc,reset_n,e	:	in	std_logic;
-	in_data			:	in	std_logic_vector (WORD_SIZE-1 downto 0);
-	i0,i1,i2		:	out	std_logic_vector (WORD_SIZE-1 downto 0);
-	out_data		:	out	std_logic_vector (WORD_SIZE-1 downto 0)
-	);
-	end pipline_gen;
-	
-	architecture bhv of pipline_gen is
-	
-	type cell_t is array (0 to (PIPLINE_LENGHT-1)) of std_logic_vector ( (WORD_SIZE-1) downto 0);
-	signal cell	:	cell_t;
-	
-	begin
-	process(clk_proc)
-	variable i		:	integer := 0;
-		begin
-		
-		if ( reset_n = '0' )	then 
-			cell <= (others =>(others => '0'));
-			
-		elsif	(rising_edge(clk_proc))	then
-			if	(e='1') then
-				cell(0) 	<= 	in_data;
-				for i in 1 to  (PIPLINE_LENGHT-1) loop
-					cell(i)	<=	cell(i-1);
-				end loop;
-				
-				out_data<=	cell(PIPLINE_LENGHT - 1);
-				i0	<=	cell(0);
-				i1	<=	cell(1);
-				i2	<=	cell(2);
-			end if;
-		end if;	
+    generic (
+        PIPLINE_LENGHT : integer;
+        WORD_SIZE : integer
+    );
+    port (
+        clk_proc :    in  std_logic;
+        reset_n  :    in  std_logic;
+        e        :    in  std_logic;
+        in_data  :    in  std_logic_vector (WORD_SIZE-1 downto 0);
+        i0,i1,i2 :    out std_logic_vector (WORD_SIZE-1 downto 0);
+        out_data :    out std_logic_vector (WORD_SIZE-1 downto 0)
+    );
+    end pipline_gen;
+
+    architecture bhv of pipline_gen is
+
+    type cell_t is array (0 to (PIPLINE_LENGHT-1)) of std_logic_vector ( (WORD_SIZE-1) downto 0);
+    signal cell    :    cell_t;
+
+    begin
+    process(clk_proc)
+    variable i        :    integer := 0;
+        begin
+
+        if ( reset_n = '0' )    then
+            cell <= (others =>(others => '0'));
+
+        elsif    (rising_edge(clk_proc))    then
+            if    (e='1') then
+                cell(0)     <=     in_data;
+                for i in 1 to  (PIPLINE_LENGHT-1) loop
+                    cell(i)    <=    cell(i-1);
+                end loop;
+
+                out_data<=    cell(PIPLINE_LENGHT - 1);
+                i0    <=    cell(0);
+                i1    <=    cell(1);
+                i2    <=    cell(2);
+            end if;
+        end if;
 end process;
 end bhv;
diff --git a/support/process/sconv/hdl/pipliner_3x3.vhd b/support/process/sconv/hdl/pipliner_3x3.vhd
index 50d13041..f03d3851 100644
--- a/support/process/sconv/hdl/pipliner_3x3.vhd
+++ b/support/process/sconv/hdl/pipliner_3x3.vhd
@@ -1,11 +1,5 @@
---||================================================================||--
---||--------  VHDL code for a 3x3 kernel image convolution ---------||--                                                       
---||----------------------------------------------------------------||--
---|| Author	: 	Kamel Eddine ABDELOUAHAB - PhD Student              ||--
---|| Institution :	Institut Pascal - DREAM team                    ||--                                          
---||                Université Blaise Pascal - Clermont Ferrand     ||--                                         
---|| Contact:	abdelouahab.kamel.eddine (at) gmail.com             ||--                                                  
---||================================================================||--
+-- Author     : K. Abdelouahab
+-- Company    : DREAM - Institut Pascal - Unviersite Clermont Auvergne
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
@@ -13,156 +7,141 @@ use IEEE.NUMERIC_STD.all;
 
 
 entity pipliner_3x3 is
-	generic (
-		LINE_WIDTH_MAX 		: integer;
-		PIX_WIDTH 			: integer
-	);
-
-		port (
-		clk_proc		: in std_logic;
-		reset_n 		: in std_logic;
-
---============================ IN FLOW =================================
-		in_data 		: in std_logic_vector((PIX_WIDTH-1) downto 0);
-		in_fv 			: in std_logic;
-		in_dv 			: in std_logic;
-
---========================  OUT CONTROL FLOW =========================== 
-		out_fv 			: out std_logic;
-		out_dv 			: out std_logic;
-		
---=========================== 3x3 MATRIX ===============================
-		p00, p01, p02 	: out std_logic_vector((PIX_WIDTH-1) downto 0);
-		p10, p11, p12 	: out std_logic_vector((PIX_WIDTH-1) downto 0);
-		p20, p21, p22 	: out std_logic_vector((PIX_WIDTH-1) downto 0);
-		
---============================= PARAMETERS =============================
-		enable_i    	: in std_logic;
-		widthimg_i 		: in std_logic_vector(15 downto 0)	
-	);
+    generic (
+        LINE_WIDTH_MAX  : integer;
+        PIX_WIDTH       : integer
+    );
+        port (
+        clk_proc        : in  std_logic;
+        reset_n         : in  std_logic;
+				enable_i        : in  std_logic;
+				widthimg_i      : in  std_logic_vector(15 downto 0);
+        in_data         : in  std_logic_vector((PIX_WIDTH-1) downto 0);
+        in_fv           : in  std_logic;
+        in_dv           : in  std_logic;
+        out_fv          : out std_logic;
+        out_dv          : out std_logic;
+        p00, p01, p02   : out std_logic_vector((PIX_WIDTH-1) downto 0);
+        p10, p11, p12   : out std_logic_vector((PIX_WIDTH-1) downto 0);
+        p20, p21, p22   : out std_logic_vector((PIX_WIDTH-1) downto 0)
+    );
 end pipliner_3x3;
 
 
 
 architecture structural of pipliner_3x3 is
 
-	signal line0_pix_out 		: std_logic_vector((PIX_WIDTH-1) downto 0);
-	signal line1_pix_out 		: std_logic_vector((PIX_WIDTH-1) downto 0);
-	
-	signal p00_s, p01_s, p02_s 	: std_logic_vector((PIX_WIDTH-1) downto 0);
-	signal p10_s, p11_s, p12_s 	: std_logic_vector((PIX_WIDTH-1) downto 0);
-	signal p20_s, p21_s, p22_s 	: std_logic_vector((PIX_WIDTH-1) downto 0);
-	
-	signal all_valid,fvs,dvs	: std_logic;
-	signal enable_reg			: std_logic;	
-	signal reset_st,reset_s		: std_logic;	
-	
-	component pipline_gen
+    signal line0_pix_out        : std_logic_vector((PIX_WIDTH-1) downto 0);
+    signal line1_pix_out        : std_logic_vector((PIX_WIDTH-1) downto 0);
+    signal p00_s, p01_s, p02_s  : std_logic_vector((PIX_WIDTH-1) downto 0);
+    signal p10_s, p11_s, p12_s  : std_logic_vector((PIX_WIDTH-1) downto 0);
+    signal p20_s, p21_s, p22_s  : std_logic_vector((PIX_WIDTH-1) downto 0);
+    signal all_valid,fvs,dvs    : std_logic;
+    signal enable_reg           : std_logic;
+    signal reset_st,reset_s     : std_logic;
+
+    component pipline_gen
 		generic (
-		PIPLINE_LENGHT			: integer;
-		WORD_SIZE				: integer	
-		);
-		
-		port (                        
-		clk_proc,reset_n,e		: in  std_logic;
-		in_data					: in  std_logic_vector (WORD_SIZE-1 downto 0);
-		i0,i1,i2				: out std_logic_vector (WORD_SIZE-1 downto 0);
-		out_data				: out std_logic_vector (WORD_SIZE-1 downto 0)
-		);
-	end component;
-	
-	
-	begin
-	
-
-	
-	enable_proc	:	process(enable_i,in_fv)
-	begin
-		if	(enable_i = '0') then	
-			reset_st	<= '0';
-		elsif(rising_edge(in_fv)) then
-			reset_st	<= '1';
-		end if;
-	end process;
-
-
-	all_valid <= in_dv and in_fv;
-	reset_s	  <=	reset_st and reset_n;
-	
-	data_pipline0 : pipline_gen
-		generic map (
-	    PIPLINE_LENGHT	=>	LINE_WIDTH_MAX-1,
-	    WORD_SIZE		=> 	PIX_WIDTH
-		)
-    	port map (
-		clk_proc	=>	clk_proc,
-		reset_n		=>	reset_s,
-		e			=>  all_valid,
-		in_data		=>	in_data,
-		i0			=>	p22,
-		i1			=>	p21,
-		i2			=>	p20,
-		out_data	=>	line0_pix_out
+        PIPLINE_LENGHT : integer;
+        WORD_SIZE : integer
+    );
+    port (
+        clk_proc :    in  std_logic;
+        reset_n  :    in  std_logic;
+        e        :    in  std_logic;
+        in_data  :    in  std_logic_vector (WORD_SIZE-1 downto 0);
+        i0,i1,i2 :    out std_logic_vector (WORD_SIZE-1 downto 0);
+        out_data :    out std_logic_vector (WORD_SIZE-1 downto 0)
+    );
+    end component;
+
+    begin
+    enable_proc    :    process(enable_i,in_fv)
+    begin
+        if (enable_i = '0') then
+            reset_st    <= '0';
+        elsif(rising_edge(in_fv)) then
+            reset_st    <= '1';
+        end if;
+    end process;
+
+    all_valid <= in_dv and in_fv;
+    reset_s   <= reset_st and reset_n;
+
+    data_pipline0 : pipline_gen
+        generic map (
+        PIPLINE_LENGHT => LINE_WIDTH_MAX-1,
+        WORD_SIZE => PIX_WIDTH
+        )
+        port map (
+        clk_proc =>  clk_proc,
+        reset_n  =>  reset_s,
+        e        =>  all_valid,
+        in_data  =>  in_data,
+        i0       =>  p22,
+        i1       =>  p21,
+        i2       =>  p20,
+        out_data =>  line0_pix_out
     );
 
-	data_pipline1 : pipline_gen
-    	generic map (
-    	PIPLINE_LENGHT	=> LINE_WIDTH_MAX-1,
-    	WORD_SIZE		=> PIX_WIDTH
-		)
-    	port map (
-		clk_proc	=>	clk_proc,
-		reset_n		=>	reset_s,
-		e			=>   all_valid,		
-		in_data		=>	line0_pix_out,
-		i0			=>	p12,
-		i1			=>	p11,
-		i2			=>	p10,
-		out_data	=>	line1_pix_out
-		);
-    
-	data_pipline2 : pipline_gen
-    	generic map (
-    	PIPLINE_LENGHT	=> 3,
-    	WORD_SIZE		=> PIX_WIDTH
-		)
-    	port map (
-		clk_proc	=>	clk_proc,
-		reset_n		=>	reset_s,
-		e			=>	all_valid,
-		in_data		=>	line1_pix_out,
-		i0			=>	p02,
-		i1			=>	p01,
-		i2			=>	p00
+    data_pipline1 : pipline_gen
+        generic map (
+        PIPLINE_LENGHT => LINE_WIDTH_MAX-1,
+        WORD_SIZE => PIX_WIDTH
+        )
+        port map (
+        clk_proc => clk_proc,
+        reset_n  => reset_s,
+        e        => all_valid,
+        in_data  => line0_pix_out,
+        i0       => p12,
+        i1       => p11,
+        i2       => p10,
+        out_data => line1_pix_out
+        );
+
+    data_pipline2 : pipline_gen
+        generic map (
+        PIPLINE_LENGHT => 3,
+        WORD_SIZE => PIX_WIDTH
+        )
+        port map (
+        clk_proc => clk_proc,
+        reset_n  => reset_s,
+        e        => all_valid,
+        in_data  => line1_pix_out,
+        i0       => p02,
+        i1       => p01,
+        i2       => p00
     );
 
-	fv_pipline		:	pipline_gen
-	 generic map (
-    	PIPLINE_LENGHT	=> LINE_WIDTH_MAX + LINE_WIDTH_MAX + 4 ,
-    	WORD_SIZE		=> 1
-		)
-		port map (
-		clk_proc	=>	clk_proc,
-		reset_n		=>	reset_s,
-		e			=>  all_valid,		
-		in_data(0)	=>	in_fv,
-		out_data(0)	=>	fvs
-		);
-
-	dv_pipline		:	pipline_gen
-	 generic map (
-    	PIPLINE_LENGHT	=> LINE_WIDTH_MAX + LINE_WIDTH_MAX +4 ,
-    	WORD_SIZE		=> 1
-		)
-		port map (
-		clk_proc	=>	clk_proc,
-		reset_n		=>	reset_s,
-		e			=>	all_valid,		
-		in_data(0)	=>	in_dv,
-		out_data(0)	=>	dvs
-		);
-	
-	out_dv	<= dvs and in_dv;
-	out_fv	<= fvs and in_fv; 
-
-	end structural;
+    fv_pipline : pipline_gen
+     generic map (
+        PIPLINE_LENGHT => LINE_WIDTH_MAX + LINE_WIDTH_MAX + 4 ,
+        WORD_SIZE => 1
+        )
+        port map (
+        clk_proc    => clk_proc,
+        reset_n     => reset_s,
+        e           => all_valid,
+        in_data(0)  => in_fv,
+        out_data(0) => fvs
+        );
+
+    dv_pipline : pipline_gen
+     generic map (
+        PIPLINE_LENGHT => LINE_WIDTH_MAX + LINE_WIDTH_MAX +4 ,
+        WORD_SIZE => 1
+        )
+        port map (
+        clk_proc    => clk_proc,
+        reset_n     => reset_s,
+        e           => all_valid,
+        in_data(0)  => in_dv,
+        out_data(0) => dvs
+        );
+
+    out_dv    <= dvs and in_dv;
+    out_fv    <= fvs and in_fv;
+
+    end structural;
diff --git a/support/process/sconv/hdl/sconv.vhd b/support/process/sconv/hdl/sconv.vhd
index fdd144de..2c7fe4c5 100644
--- a/support/process/sconv/hdl/sconv.vhd
+++ b/support/process/sconv/hdl/sconv.vhd
@@ -1,11 +1,5 @@
---||================================================================||--
---||-------  VHDL code for a 3x3 kernel image convolution --------- ||--                                                       
---||----------------------------------------------------------------||--
---|| Author	: 	Kamel Eddine ABDELOUAHAB - PhD Student              ||--
---|| Institution :	Institut Pascal - DREAM team                    ||--                                          
---||                Université Blaise Pascal - Clermont Ferrand     ||--                                         
---|| Contact:	ke.abdelouahab(at) gmail.com                        ||--                                                  
---||================================================================||--
+-- Author     : K. Abdelouahab
+-- Company    : DREAM - Institut Pascal - Unviersite Clermont Auvergne
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
@@ -13,166 +7,131 @@ use IEEE.NUMERIC_STD.all;
 
 
 entity sconv is
-	generic (
-		LINE_WIDTH_MAX 	: integer	:=	320;
-		IN_SIZE 		: integer	:=	8;
-		OUT_SIZE 		: integer	:=	8;
-		CLK_PROC_FREQ 	: integer 	:=  48000000
-	);
-	port (
-		clk_proc 	: in std_logic;
-		reset_n 	: in std_logic;
-
---============================ IN FLOW =================================
-		in_data 	: in std_logic_vector((IN_SIZE-1) downto 0);
-		in_fv 		: in std_logic;
-		in_dv 		: in std_logic;
-
---=========================== OUT FLOW =================================
-		out_data 	: out std_logic_vector((OUT_SIZE-1) downto 0);
-		out_fv 		: out std_logic;
-		out_dv 		: out std_logic;
-
---============================ Slaves =================================
-		addr_rel_i 	: in std_logic_vector(3 downto 0);
-		wr_i 		: in std_logic;
-		rd_i 		: in std_logic;
-		datawr_i 	: in std_logic_vector(31 downto 0);
-		datard_o 	: out std_logic_vector(31 downto 0)
-	);
+  generic (
+    LINE_WIDTH_MAX : integer  :=  320;
+    IN_SIZE        : integer  :=  8;
+    OUT_SIZE       : integer  :=  8;
+    CLK_PROC_FREQ  : integer  :=  48000000
+  );
+  port (
+    clk_proc   : in std_logic;
+    reset_n    : in std_logic;
+    in_data    : in std_logic_vector((IN_SIZE-1) downto 0);
+    in_fv      : in std_logic;
+    in_dv      : in std_logic;
+    addr_rel_i : in std_logic_vector(3 downto 0);
+    wr_i       : in std_logic;
+    rd_i       : in std_logic;
+    datawr_i   : in std_logic_vector(31 downto 0);
+    out_data   : out std_logic_vector((OUT_SIZE-1) downto 0);
+    out_fv     : out std_logic;
+    out_dv     : out std_logic;
+    datard_o   : out std_logic_vector(31 downto 0)
+  );
 end sconv;
 
 architecture rtl of sconv is
 
-component conv_slave
-	port (
-		clk_proc		: in std_logic;
-		reset_n			: in std_logic;
-		
-		------------------------- bus_sl ------------------------
-		addr_rel_i		: in std_logic_vector(3 downto 0);
-		wr_i			: in std_logic;
-		rd_i			: in std_logic;
-		datawr_i		: in std_logic_vector(31 downto 0);
-		datard_o		: out std_logic_vector(31 downto 0);
-		
-		--------------- connections to conv module--------------------
-		enable_o		: out std_logic;
-		widthimg_o		: out std_logic_vector(15 downto 0);
-		
-		------------------------ weights----------------------------
-		w11_o			: out std_logic_vector (7 downto 0);
-		w12_o			: out std_logic_vector (7 downto 0);
-		w13_o			: out std_logic_vector (7 downto 0);
-		w21_o			: out std_logic_vector (7 downto 0);
-		w22_o			: out std_logic_vector (7 downto 0);
-		w23_o			: out std_logic_vector (7 downto 0);
-		w31_o			: out std_logic_vector (7 downto 0);
-		w32_o			: out std_logic_vector (7 downto 0);
-		w33_o			: out std_logic_vector (7 downto 0);
-		norm_o			: out std_logic_vector (7 downto 0)
-	);
-end component;
-
-component conv_process
-	generic (
-		LINE_WIDTH_MAX	: integer;
-		PIX_WIDTH 		: integer
-	);
-	port (
-		clk_proc	: in std_logic;
-		reset_n		: in std_logic;
-
-		------------------------- in flow -----------------------
-		in_data		: in std_logic_vector((PIX_WIDTH-1) downto 0);
-		in_fv		: in std_logic;
-		in_dv		: in std_logic;
-
-     --------------------------- in kernel-----------------------------
-		w11,w12,w13	:	in std_logic_vector ((PIX_WIDTH-1) downto 0);
-		w21,w22,w23	:	in std_logic_vector ((PIX_WIDTH-1) downto 0);
-		w31,w32,w33	:	in std_logic_vector ((PIX_WIDTH-1) downto 0);
-		norm		: 	in std_logic_vector ((PIX_WIDTH-1) downto 0);		
-
-		------------------------ out flow -----------------------
-		out_data	: out std_logic_vector((PIX_WIDTH-1) downto 0);
-		out_fv		: out std_logic;
-		out_dv		: out std_logic;
+  component conv_slave
+  port (
+    clk_proc   : in std_logic;
+    reset_n    : in std_logic;
+    addr_rel_i : in std_logic_vector(3 downto 0);
+    wr_i       : in std_logic;
+    rd_i       : in std_logic;
+    datawr_i   : in std_logic_vector(31 downto 0);
+    datard_o   : out std_logic_vector(31 downto 0);
+    enable_o   : out std_logic;
+    widthimg_o : out std_logic_vector(15 downto 0);
+    w11_o      : out std_logic_vector (7 downto 0);
+    w12_o      : out std_logic_vector (7 downto 0);
+    w13_o      : out std_logic_vector (7 downto 0);
+    w21_o      : out std_logic_vector (7 downto 0);
+    w22_o      : out std_logic_vector (7 downto 0);
+    w23_o      : out std_logic_vector (7 downto 0);
+    w31_o      : out std_logic_vector (7 downto 0);
+    w32_o      : out std_logic_vector (7 downto 0);
+    w33_o      : out std_logic_vector (7 downto 0);
+    norm_o     : out std_logic_vector (7 downto 0)
+  );
+  end component;
+
+  component conv_process
+  generic (
+    LINE_WIDTH_MAX: integer;
+    PIX_WIDTH     : integer
+  );
+  port(
+    clk_proc    : in  std_logic;
+    reset_n     : in  std_logic;
+    in_data     : in  std_logic_vector((PIX_WIDTH-1) downto 0);
+    in_fv       : in  std_logic;
+    in_dv       : in  std_logic;
+    w11,w12,w13 : in  std_logic_vector ((PIX_WIDTH-1) downto 0);
+    w21,w22,w23 : in  std_logic_vector ((PIX_WIDTH-1) downto 0);
+    w31,w32,w33 : in  std_logic_vector ((PIX_WIDTH-1) downto 0);
+    norm        : in  std_logic_vector ((PIX_WIDTH-1) downto 0);
+    enable_i    : in  std_logic;
+    widthimg_i  : in  std_logic_vector(15 downto 0);
+    out_data    : out std_logic_vector (PIX_WIDTH-1 downto 0);
+    out_fv      : out std_logic;
+    out_dv      : out std_logic
+    );
+  end component;
+
+
+  signal  enable_s       : std_logic;
+  signal  widthimg_s     : std_logic_vector(15 downto 0);
+  signal  w11s,w12s,w13s : std_logic_vector (IN_SIZE-1 downto 0);
+  signal  w21s,w22s,w23s : std_logic_vector (IN_SIZE-1 downto 0);
+  signal  w31s,w32s,w33s : std_logic_vector (IN_SIZE-1 downto 0);
+  signal  norms          : std_logic_vector (IN_SIZE-1 downto 0);
 
-		
-		------------------------- params ------------------------
-		enable_i	: in std_logic;
-		widthimg_i	: in std_logic_vector(15 downto 0)
-	);
-end component;
-
-	
--- signals part
-	signal 	enable_s 		: std_logic;
-	signal 	widthimg_s 		: std_logic_vector(15 downto 0);
-	signal 	w11s,w12s,w13s	: std_logic_vector (IN_SIZE-1 downto 0);
-	signal	w21s,w22s,w23s	: std_logic_vector (IN_SIZE-1 downto 0);
-	signal	w31s,w32s,w33s	: std_logic_vector (IN_SIZE-1 downto 0);
-	signal	norms			: std_logic_vector (IN_SIZE-1 downto 0);
-	
 begin
 
-	conv_slave_inst : conv_slave
+  conv_slave_inst : conv_slave
     port map (
-		clk_proc	=>	clk_proc,
-		reset_n		=>	reset_n,
-
-		-- bus_sl
-		addr_rel_i	=>	addr_rel_i,
-		wr_i		=>	wr_i,
-		rd_i		=>	rd_i,
-		datawr_i	=>	datawr_i,
-		datard_o	=>	datard_o,
-
-		-- connections to conv_process
-		enable_o	=>	enable_s,
-		widthimg_o	=>	widthimg_s,
-		
-		-- kernel value
-		w11_o		=> w11s,
-		w12_o		=> w12s,
-		w13_o		=> w13s,
-		w21_o		=> w21s,
-		w22_o		=> w22s,
-		w23_o		=> w23s,
-		w31_o		=> w31s,
-		w32_o		=> w32s,
-		w33_o		=> w33s,
-		norm_o		=> norms
-	);
-
-	conv_process_inst : conv_process
+    clk_proc   => clk_proc,
+    reset_n    => reset_n,
+    addr_rel_i => addr_rel_i,
+    wr_i       => wr_i,
+    rd_i       => rd_i,
+    datawr_i   => datawr_i,
+    datard_o   => datard_o,
+    enable_o   => enable_s,
+    widthimg_o => widthimg_s,
+    w11_o      => w11s,
+    w12_o      => w12s,
+    w13_o      => w13s,
+    w21_o      => w21s,
+    w22_o      => w22s,
+    w23_o      => w23s,
+    w31_o      => w31s,
+    w32_o      => w32s,
+    w33_o      => w33s,
+    norm_o     => norms
+  );
+
+  conv_process_inst : conv_process
     generic map (
-    	LINE_WIDTH_MAX	=>	LINE_WIDTH_MAX,
-    	PIX_WIDTH		=>	IN_SIZE
-	)
+      LINE_WIDTH_MAX  =>  LINE_WIDTH_MAX,
+      PIX_WIDTH    =>  IN_SIZE
+  )
     port map (
-		clk_proc	=>	clk_proc,
-		reset_n		=>	reset_n,
---============================ IN FLOW =============================
-		in_data		=>	in_data,
-		in_fv		=>	in_fv,
-		in_dv		=>	in_dv,
-
---============================ IN KERNEL ===========================
-		w11 => w11s	,	w12 => w12s	,	w13 => w13s,	
-		w21 => w21s	,	w22 => w22s	,	w23 => w23s,	
-		w31 => w31s	,	w32 => w32s	,	w33 => w33s,
-
---============================ OUT FLOW ============================
-		out_data	=>	out_data,
-		out_fv		=>	out_fv,
-		out_dv		=>	out_dv,
-		norm		=>	norms,
-
---============================ PARAMS ==============================
-		enable_i	=>	enable_s,
-		widthimg_i	=>	widthimg_s
-	);
+    clk_proc   =>  clk_proc,
+    reset_n    =>  reset_n,
+    in_data    =>  in_data,
+    in_fv      =>  in_fv,
+    in_dv      =>  in_dv,
+		out_data   =>  out_data,
+		out_fv     =>  out_fv,
+		out_dv     =>  out_dv,
+		norm       =>  norms,
+		enable_i   =>  enable_s,
+		widthimg_i =>  widthimg_s,
+    w11 => w11s, w12 => w12s, w13 => w13s,
+    w21 => w21s, w22 => w22s, w23 => w23s,
+    w31 => w31s, w32 => w32s, w33 => w33s
+  );
 
 end rtl;
diff --git a/support/process/sconv/hdl/sconv_process.vhd b/support/process/sconv/hdl/sconv_process.vhd
index cee5323e..f3bb17e6 100644
--- a/support/process/sconv/hdl/sconv_process.vhd
+++ b/support/process/sconv/hdl/sconv_process.vhd
@@ -1,160 +1,129 @@
---||================================================================||--
---||-------  VHDL code for a 3x3 kernel image convolution --------- ||--                                                       
---||----------------------------------------------------------------||--
---|| Author	: 	Kamel Eddine ABDELOUAHAB - PhD Student              ||--
---|| Institution :	Institut Pascal - DREAM team                    ||--                                          
---||                Université Blaise Pascal - Clermont Ferrand     ||--                                         
---|| Contact:	abdelouahab.kamel.eddine (at) gmail.com             ||--                                                  
---||================================================================||--
+-- Author     : K. Abdelouahab
+-- Company    : DREAM - Institut Pascal - Unviersite Clermont Auvergne
 
 library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
 
 entity conv_process is
-
-		generic (
-			LINE_WIDTH_MAX 	: integer;
-			PIX_WIDTH 	: integer
-		);
-		
-		port(
-			clk_proc 		: in std_logic;
-			reset_n 		: in std_logic;
-	
---============================ IN FLOW =================================		
-			in_data 		: in std_logic_vector((PIX_WIDTH-1) downto 0);
-			in_fv 			: in std_logic;
-			in_dv 			: in std_logic;
-
---============================ IN KERNEL ===============================
-			w11,w12,w13		: in std_logic_vector ((PIX_WIDTH-1) downto 0);
-			w21,w22,w23		: in std_logic_vector ((PIX_WIDTH-1) downto 0);
-			w31,w32,w33		: in std_logic_vector ((PIX_WIDTH-1) downto 0);
-			norm			: in std_logic_vector ((PIX_WIDTH-1) downto 0);
-		
---============================ OUT FLOW =================================-
-			out_data		: out	std_logic_vector (PIX_WIDTH-1 downto 0);
-			out_fv			: out	std_logic;
-			out_dv			: out	std_logic;
-
---============================ PARAMS ==================================
-			enable_i 		: in std_logic;
-			widthimg_i 		: in std_logic_vector(15 downto 0)
-			);
+generic (
+    LINE_WIDTH_MAX     : integer;
+    PIX_WIDTH     : integer
+);
+port(
+    clk_proc    : in  std_logic;
+    reset_n     : in  std_logic;
+    in_data     : in  std_logic_vector((PIX_WIDTH-1) downto 0);
+    in_fv       : in  std_logic;
+    in_dv       : in  std_logic;
+    w11,w12,w13 : in  std_logic_vector ((PIX_WIDTH-1) downto 0);
+    w21,w22,w23 : in  std_logic_vector ((PIX_WIDTH-1) downto 0);
+    w31,w32,w33 : in  std_logic_vector ((PIX_WIDTH-1) downto 0);
+    norm        : in  std_logic_vector ((PIX_WIDTH-1) downto 0);
+    enable_i    : in  std_logic;
+    widthimg_i  : in  std_logic_vector(15 downto 0);
+    out_data    : out std_logic_vector (PIX_WIDTH-1 downto 0);
+    out_fv      : out std_logic;
+    out_dv      : out std_logic
+    );
 end conv_process;
 
 
 architecture DataFlow of conv_process is
-	signal 	i00,i01,i02 	: std_logic_vector (PIX_WIDTH-1 downto 0);
-	signal	i10,i11,i12		: std_logic_vector (PIX_WIDTH-1 downto 0);
-	signal	i20,i21,i22		: std_logic_vector (PIX_WIDTH-1 downto 0); 
+    signal i00, i01, i02 : std_logic_vector (PIX_WIDTH-1 downto 0);
+    signal i10, i11, i12 : std_logic_vector (PIX_WIDTH-1 downto 0);
+    signal i20, i21, i22 : std_logic_vector (PIX_WIDTH-1 downto 0);
+    signal out_dvp       : std_logic;
+    signal out_fvp       : std_logic;
+
+    component kernel_3x3
+    generic(
+        PIX_WIDTH :  integer
+    );
+    port (
+        reset_n           : in  std_logic;
+        clk_proc          : in  std_logic;
+        in_dv             : in  std_logic;
+        in_fv             : in  std_logic;
+        enable_i          : in  std_logic;
+        p11,p12,p13       : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        p21,p22,p23       : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        p31,p32,p33       : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        ker11,ker12,ker13 : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        ker21,ker22,ker23 : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        ker31,ker32,ker33 : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        norm              : in  std_logic_vector(PIX_WIDTH-1 downto 0);
+        out_data          : out std_logic_vector(PIX_WIDTH-1 downto 0);
+        out_dv            : out std_logic;
+        out_fv            : out std_logic
+        );
+    end component;
+
+    component pipliner_3x3
+    generic (
+        LINE_WIDTH_MAX  : integer;
+        PIX_WIDTH       : integer
+    );
+        port (
+        clk_proc        : in  std_logic;
+        reset_n         : in  std_logic;
+        enable_i        : in  std_logic;
+        widthimg_i      : in  std_logic_vector(15 downto 0);
+        in_data         : in  std_logic_vector((PIX_WIDTH-1) downto 0);
+        in_fv           : in  std_logic;
+        in_dv           : in  std_logic;
+        out_fv          : out std_logic;
+        out_dv          : out std_logic;
+        p00, p01, p02   : out std_logic_vector((PIX_WIDTH-1) downto 0);
+        p10, p11, p12   : out std_logic_vector((PIX_WIDTH-1) downto 0);
+        p20, p21, p22   : out std_logic_vector((PIX_WIDTH-1) downto 0)
+    );
+    end component;
 
-	signal	out_dvp,out_fvp	: std_logic;
-	
-	component kernel_3x3
-		generic(
-		PIX_WIDTH	: integer
-		);
-		
-		port(
-		clk_proc,reset_n	:	in	std_logic;
-		in_fv,in_dv			:	in	std_logic;
-		enable_i			:	in	std_logic;
+    ------------------------------------------------------------------------------
+    begin
+    inst_pipliner    :    pipliner_3x3
+        generic map(
+        LINE_WIDTH_MAX => LINE_WIDTH_MAX,
+        PIX_WIDTH => PIX_WIDTH
+        )
 
-		p11,p12,p13			:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		p21,p22,p23			:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		p31,p32,p33			:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		
-		ker11,ker12,ker13	:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		ker21,ker22,ker23	:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		ker31,ker32,ker33	:	in	std_logic_vector(PIX_WIDTH-1 downto 0);
-		norm				:	in 	std_logic_vector(PIX_WIDTH-1 downto 0);		
-		
-		out_data			:	out	std_logic_vector(PIX_WIDTH-1 downto 0);
-		out_fv,out_dv		:	out	std_logic		
-		);
-	end component;
-	
-	component pipliner_3x3
-		generic (
-			LINE_WIDTH_MAX 	: integer;
-			PIX_WIDTH 		: integer
-		);
-	
-		port (
-		clk_proc		: in std_logic;
-		reset_n 		: in std_logic;
+        port map (
+        clk_proc   => clk_proc,
+        reset_n    => reset_n,
+        in_data    => in_data,
+        in_fv      => in_fv,
+        in_dv      => in_dv,
+        out_fv     => out_fvp,
+        out_dv     => out_dvp,
+        enable_i   => enable_i ,
+        widthimg_i => widthimg_i,
+        p00 => i00, p01 => i01, p02 => i02,
+        p10 => i10, p11 => i11, p12 => i12,
+        p20 => i20, p21 => i21, p22 => i22
+        );
 
---============================ IN FLOW =================================
-		in_data 		: in std_logic_vector((PIX_WIDTH-1) downto 0);
-		in_fv 			: in std_logic;
-		in_dv 			: in std_logic;
 
---========================  OUT CONTROL FLOW =========================== 
-		out_fv 			: out std_logic;
-		out_dv 			: out std_logic;
-		
---=========================== 3x3 MATRIX ============================
-		p00, p01, p02 	: out std_logic_vector((PIX_WIDTH-1) downto 0);
-		p10, p11, p12 	: out std_logic_vector((PIX_WIDTH-1) downto 0);
-		p20, p21, p22 	: out std_logic_vector((PIX_WIDTH-1) downto 0);
-		
---============================= PARAMETERS =============================
-		enable_i    	: in std_logic;
-		widthimg_i 		: in std_logic_vector(15 downto 0)
-		
-	);
-	end component;
-	
-	begin
-	
-	
-	inst_pipliner	:	pipliner_3x3	
-		generic map(
-		LINE_WIDTH_MAX 	=> LINE_WIDTH_MAX,
-		PIX_WIDTH 		=> PIX_WIDTH 		 
-		)
-		
-		port map (
-		clk_proc=>	clk_proc 	,						
-		reset_n =>	reset_n ,				
-		in_data	=>	in_data ,				
-		in_fv 	=>	in_fv ,					
-		in_dv 	=>	in_dv ,				
-		out_fv 	=>	out_fvp,		
-		out_dv 	=>	out_dvp,			
-		p00 => i00	,	 p01 => i01 	,	 p02 => i02, 	
-		p10 => i10	,	 p11 => i11 	,	 p12 => i12, 	
-		p20 => i20	,	 p21 => i21 	,	 p22 => i22 ,
-		enable_i    =>	enable_i ,   	
-		widthimg_i 	=>	widthimg_i 	
-		);
-	
-	
-	inst_ker		:	kernel_3x3	
-		generic map(
-		PIX_WIDTH	=>	PIX_WIDTH
-		)	
-		port map	(		
-		clk_proc	=>	clk_proc,
-		reset_n		=>	reset_n,	
-		in_fv		=>	out_fvp,
-		in_dv		=>	out_dvp,	
-        enable_i	=>	enable_i,			
-		
-		p11	=> i00	,	p12	=> i01	,	p13	=> i02,			
-		p21	=> i10	,	p22	=> i11	,	p23	=> i12,			
-		p31	=> i20	,	p32	=> i21	,	p33	=> i22,			
-		
-		ker11 => w11,	ker12 => w12,	ker13 => w13,	
-		ker21 => w21,	ker22 => w22,	ker23 => w23,	
-		ker31 => w31,	ker32 => w32,	ker33 => w33,	
-		norm  => norm,
-		
-		out_data	=> out_data,			
-		out_fv		=> out_fv,
-		out_dv		=> out_dv		
-		);
+    inst_ker        :    kernel_3x3
+        generic map(
+        PIX_WIDTH => PIX_WIDTH
+        )
+        port map(
+        clk_proc => clk_proc,
+        reset_n  => reset_n,
+        in_fv    => out_fvp,
+        in_dv    => out_dvp,
+        enable_i => enable_i,
+        norm     => norm,
+        out_data => out_data,
+        out_fv   => out_fv,
+        out_dv   => out_dv,
+        p11   => i00, p12   => i01, p13   => i02,
+        p21   => i10, p22   => i11, p23   => i12,
+        p31   => i20, p32   => i21, p33   => i22,
+        ker11 => w11, ker12 => w12, ker13 => w13,
+        ker21 => w21, ker22 => w22, ker23 => w23,
+        ker31 => w31, ker32 => w32, ker33 => w33
+        );
 
-	end DataFlow;	
+    end DataFlow;
diff --git a/support/process/sconv/hdl/sconv_slave.vhd b/support/process/sconv/hdl/sconv_slave.vhd
index 7a867170..036f2226 100644
--- a/support/process/sconv/hdl/sconv_slave.vhd
+++ b/support/process/sconv/hdl/sconv_slave.vhd
@@ -1,113 +1,102 @@
+-- Author     : K. Abdelouahab
+-- Company    : DREAM - Institut Pascal - Unviersite Clermont Auvergne
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.NUMERIC_STD.all;
 
 entity conv_slave is
-	port (
-		clk_proc		: in std_logic;
-		reset_n			: in std_logic;
-		
-		------------------------- bus_sl ------------------------
-		addr_rel_i		: in std_logic_vector(3 downto 0);
-		wr_i			: in std_logic;
-		rd_i			: in std_logic;
-		datawr_i		: in std_logic_vector(31 downto 0);
-		datard_o		: out std_logic_vector(31 downto 0);
-		
-		--------------- connections to conv module--------------------
-		enable_o		: out std_logic;
-		widthimg_o		: out std_logic_vector(15 downto 0);
-		
-		------------------------ weights----------------------------
-		w11_o			: out std_logic_vector (7 downto 0);
-		w12_o			: out std_logic_vector (7 downto 0);
-		w13_o			: out std_logic_vector (7 downto 0);
-		w21_o			: out std_logic_vector (7 downto 0);
-		w22_o			: out std_logic_vector (7 downto 0);
-		w23_o			: out std_logic_vector (7 downto 0);
-		w31_o			: out std_logic_vector (7 downto 0);
-		w32_o			: out std_logic_vector (7 downto 0);
-		w33_o			: out std_logic_vector (7 downto 0);
-		norm_o			: out std_logic_vector (7 downto 0)
-	);
+port (
+    clk_proc   : in std_logic;
+    reset_n    : in std_logic;
+    addr_rel_i : in std_logic_vector(3 downto 0);
+    wr_i       : in std_logic;
+    rd_i       : in std_logic;
+    datawr_i   : in std_logic_vector(31 downto 0);
+    datard_o   : out std_logic_vector(31 downto 0);
+    enable_o   : out std_logic;
+    widthimg_o : out std_logic_vector(15 downto 0);
+    w11_o      : out std_logic_vector (7 downto 0);
+    w12_o      : out std_logic_vector (7 downto 0);
+    w13_o      : out std_logic_vector (7 downto 0);
+    w21_o      : out std_logic_vector (7 downto 0);
+    w22_o      : out std_logic_vector (7 downto 0);
+    w23_o      : out std_logic_vector (7 downto 0);
+    w31_o      : out std_logic_vector (7 downto 0);
+    w32_o      : out std_logic_vector (7 downto 0);
+    w33_o      : out std_logic_vector (7 downto 0);
+    norm_o     : out std_logic_vector (7 downto 0)
+  );
 end conv_slave;
 
 architecture rtl of conv_slave is
 
-	constant ENABLE_REG_ADDR	: natural := 0;
-	constant WIDTHIMG_REG_ADDR	: natural := 1;
-	constant W11_ADDR			: natural := 2;
-	constant W12_ADDR			: natural := 3;
-	constant W13_ADDR			: natural := 4;
-	constant W21_ADDR			: natural := 5;
-	constant W22_ADDR			: natural := 6;
-	constant W23_ADDR			: natural := 7;
-	constant W31_ADDR			: natural := 8;
-	constant W32_ADDR			: natural := 9;
-	constant W33_ADDR			: natural := 10;
-	constant NORM_ADDR			: natural := 11;
-	
-	
-	
-	signal enable_reg 			: std_logic;
-	signal widthimg_reg 		: std_logic_vector(15 downto 0);
-	signal w11_reg				: std_logic_vector(7 downto 0);
-	signal w12_reg				: std_logic_vector(7 downto 0);
-	signal w13_reg				: std_logic_vector(7 downto 0);
-	signal w21_reg				: std_logic_vector(7 downto 0);
-	signal w22_reg				: std_logic_vector(7 downto 0);
-	signal w23_reg				: std_logic_vector(7 downto 0);
-	signal w31_reg				: std_logic_vector(7 downto 0);
-	signal w32_reg				: std_logic_vector(7 downto 0);
-	signal w33_reg				: std_logic_vector(7 downto 0);
-	signal norm_reg				: std_logic_vector(7 downto 0);
-	
+  constant ENABLE_REG_ADDR  : natural := 0;
+  constant WIDTHIMG_REG_ADDR  : natural := 1;
+  constant W11_ADDR  : natural := 2;
+  constant W12_ADDR  : natural := 3;
+  constant W13_ADDR  : natural := 4;
+  constant W21_ADDR  : natural := 5;
+  constant W22_ADDR  : natural := 6;
+  constant W23_ADDR  : natural := 7;
+  constant W31_ADDR  : natural := 8;
+  constant W32_ADDR  : natural := 9;
+  constant W33_ADDR  : natural := 10;
+  constant NORM_ADDR : natural := 11;
+
+  signal enable_reg     : std_logic;
+  signal widthimg_reg   : std_logic_vector(15 downto 0);
+  signal w11_reg        : std_logic_vector(7 downto 0);
+  signal w12_reg        : std_logic_vector(7 downto 0);
+  signal w13_reg        : std_logic_vector(7 downto 0);
+  signal w21_reg        : std_logic_vector(7 downto 0);
+  signal w22_reg        : std_logic_vector(7 downto 0);
+  signal w23_reg        : std_logic_vector(7 downto 0);
+  signal w31_reg        : std_logic_vector(7 downto 0);
+  signal w32_reg        : std_logic_vector(7 downto 0);
+  signal w33_reg        : std_logic_vector(7 downto 0);
+  signal norm_reg       : std_logic_vector(7 downto 0);
 
 begin
+  write_reg : process (clk_proc, reset_n)
+  begin
+    if(reset_n='0') then
+      enable_reg <= '0';
+      widthimg_reg <= std_logic_vector(to_unsigned(320, 16));
+
+    elsif(rising_edge(clk_proc)) then
+      if(wr_i='1') then
+      case addr_rel_i is
+        when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 4))   =>  enable_reg     <= datawr_i(0);
+        when std_logic_vector(to_unsigned(WIDTHIMG_REG_ADDR, 4)) =>  widthimg_reg   <= datawr_i(15 downto 0);
+        when std_logic_vector(to_unsigned(W11_ADDR, 4))          =>  w11_reg        <= datawr_i (7 downto 0);
+        when std_logic_vector(to_unsigned(W12_ADDR, 4))          =>  w12_reg        <= datawr_i (7 downto 0);
+        when std_logic_vector(to_unsigned(W13_ADDR, 4))          =>  w13_reg        <= datawr_i (7 downto 0);
+        when std_logic_vector(to_unsigned(W21_ADDR, 4))          =>  w21_reg        <= datawr_i (7 downto 0);
+        when std_logic_vector(to_unsigned(W22_ADDR, 4))          =>  w22_reg        <= datawr_i (7 downto 0);
+        when std_logic_vector(to_unsigned(W23_ADDR, 4))          =>  w23_reg        <= datawr_i (7 downto 0);
+        when std_logic_vector(to_unsigned(W31_ADDR, 4))          =>  w31_reg        <= datawr_i (7 downto 0);
+        when std_logic_vector(to_unsigned(W32_ADDR, 4))          =>  w32_reg        <= datawr_i (7 downto 0);
+        when std_logic_vector(to_unsigned(W33_ADDR, 4))          =>  w33_reg        <= datawr_i (7 downto 0);
+        when std_logic_vector(to_unsigned(NORM_ADDR, 4))         =>  norm_reg       <= datawr_i (7 downto 0);
 
-	write_reg : process (clk_proc, reset_n)
-	begin
-		if(reset_n='0') then
-			enable_reg <= '0';
-			widthimg_reg <= std_logic_vector(to_unsigned(320, 16));
-			
-			
-		elsif(rising_edge(clk_proc)) then
-			if(wr_i='1') then
-			case addr_rel_i is
-				when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 4))	=>	enable_reg 		<= datawr_i(0);
-				when std_logic_vector(to_unsigned(WIDTHIMG_REG_ADDR, 4))=>	widthimg_reg 	<= datawr_i(15 downto 0);
+        when others=>
+        end case;
+      end if;
+    end if;
+  end process;
 
-				when std_logic_vector(to_unsigned(W11_ADDR, 4))			=>	w11_reg	<= datawr_i (7 downto 0);	
-				when std_logic_vector(to_unsigned(W12_ADDR, 4))			=>	w12_reg	<= datawr_i (7 downto 0);
-				when std_logic_vector(to_unsigned(W13_ADDR, 4))			=>	w13_reg	<= datawr_i (7 downto 0);
-				when std_logic_vector(to_unsigned(W21_ADDR, 4))			=>	w21_reg	<= datawr_i (7 downto 0);
-				when std_logic_vector(to_unsigned(W22_ADDR, 4))			=>	w22_reg	<= datawr_i (7 downto 0);
-				when std_logic_vector(to_unsigned(W23_ADDR, 4))			=>	w23_reg	<= datawr_i (7 downto 0);
-				when std_logic_vector(to_unsigned(W31_ADDR, 4))			=>	w31_reg	<= datawr_i (7 downto 0);
-				when std_logic_vector(to_unsigned(W32_ADDR, 4))			=>	w32_reg	<= datawr_i (7 downto 0);
-				when std_logic_vector(to_unsigned(W33_ADDR, 4))			=>	w33_reg	<= datawr_i (7 downto 0);
-				when std_logic_vector(to_unsigned(NORM_ADDR, 4))		=>	norm_reg	<= datawr_i (7 downto 0);
-					
-				when others=>
-				end case;
-			end if;
-		end if;
-	end process;
-	
-	enable_o 	<= enable_reg;
-	widthimg_o 	<= widthimg_reg;
+  enable_o   <= enable_reg;
+  widthimg_o <= widthimg_reg;
+  w11_o      <=  w11_reg;
+  w12_o      <=  w12_reg;
+  w13_o      <=  w13_reg;
+  w21_o      <=  w21_reg;
+  w22_o      <=  w22_reg;
+  w23_o      <=  w23_reg;
+  w31_o      <=  w31_reg;
+  w32_o      <=  w32_reg;
+  w33_o      <=  w33_reg;
+  norm_o     <=  norm_reg;
 
-	w11_o		<=	w11_reg;
-	w12_o		<=	w12_reg;
-	w13_o		<=	w13_reg;
-	w21_o		<=	w21_reg;
-	w22_o		<=	w22_reg;
-	w23_o		<=	w23_reg;
-	w31_o		<=	w31_reg;
-	w32_o		<=	w32_reg;
-	w33_o		<=	w33_reg;
-	norm_o		<=	norm_reg;
-	
-	
 end rtl;