1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PGTABLE_H
3#define _ASM_X86_PGTABLE_H
4
5#include <linux/mem_encrypt.h>
6#include <asm/page.h>
7#include <asm/pgtable_types.h>
8
9/*
10 * Macro to mark a page protection value as UC-
11 */
12#define pgprot_noncached(prot) \
13 ((boot_cpu_data.x86 > 3) \
14 ? (__pgprot(pgprot_val(prot) | \
15 cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS))) \
16 : (prot))
17
18#ifndef __ASSEMBLER__
19#include <linux/spinlock.h>
20#include <asm/x86_init.h>
21#include <asm/pkru.h>
22#include <asm/fpu/api.h>
23#include <asm/coco.h>
24#include <asm-generic/pgtable_uffd.h>
25#include <linux/page_table_check.h>
26
27extern pgd_t early_top_pgt[PTRS_PER_PGD];
28bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd);
29
30struct seq_file;
31void ptdump_walk_pgd_level(struct seq_file *m, struct mm_struct *mm);
32void ptdump_walk_pgd_level_debugfs(struct seq_file *m, struct mm_struct *mm,
33 bool user);
34bool ptdump_walk_pgd_level_checkwx(void);
35#define ptdump_check_wx ptdump_walk_pgd_level_checkwx
36void ptdump_walk_user_pgd_level_checkwx(void);
37
38/*
39 * Macros to add or remove encryption attribute
40 */
41#define pgprot_encrypted(prot) __pgprot(cc_mkenc(pgprot_val(prot)))
42#define pgprot_decrypted(prot) __pgprot(cc_mkdec(pgprot_val(prot)))
43
44#ifdef CONFIG_DEBUG_WX
45#define debug_checkwx_user() ptdump_walk_user_pgd_level_checkwx()
46#else
47#define debug_checkwx_user() do { } while (0)
48#endif
49
50/*
51 * ZERO_PAGE is a global shared page that is always zero: used
52 * for zero-mapped memory areas etc..
53 */
54extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
55 __visible;
56#define ZERO_PAGE(vaddr) ((void)(vaddr),virt_to_page(empty_zero_page))
57
58extern spinlock_t pgd_lock;
59extern struct list_head pgd_list;
60
61extern struct mm_struct *pgd_page_get_mm(struct page *page);
62
63extern pmdval_t early_pmd_flags;
64
65#ifdef CONFIG_PARAVIRT_XXL
66#include <asm/paravirt.h>
67#else /* !CONFIG_PARAVIRT_XXL */
68#define set_pte(ptep, pte) native_set_pte(ptep, pte)
69
70#define set_pte_atomic(ptep, pte) \
71 native_set_pte_atomic(ptep, pte)
72
73#define set_pmd(pmdp, pmd) native_set_pmd(pmdp, pmd)
74
75#ifndef __PAGETABLE_P4D_FOLDED
76#define set_pgd(pgdp, pgd) native_set_pgd(pgdp, pgd)
77#define pgd_clear(pgd) (pgtable_l5_enabled() ? native_pgd_clear(pgd) : 0)
78#endif
79
80#ifndef set_p4d
81# define set_p4d(p4dp, p4d) native_set_p4d(p4dp, p4d)
82#endif
83
84#ifndef __PAGETABLE_PUD_FOLDED
85#define p4d_clear(p4d) native_p4d_clear(p4d)
86#endif
87
88#ifndef set_pud
89# define set_pud(pudp, pud) native_set_pud(pudp, pud)
90#endif
91
92#ifndef __PAGETABLE_PUD_FOLDED
93#define pud_clear(pud) native_pud_clear(pud)
94#endif
95
96#define pte_clear(mm, addr, ptep) native_pte_clear(mm, addr, ptep)
97#define pmd_clear(pmd) native_pmd_clear(pmd)
98
99#define pgd_val(x) native_pgd_val(x)
100#define __pgd(x) native_make_pgd(x)
101
102#ifndef __PAGETABLE_P4D_FOLDED
103#define p4d_val(x) native_p4d_val(x)
104#define __p4d(x) native_make_p4d(x)
105#endif
106
107#ifndef __PAGETABLE_PUD_FOLDED
108#define pud_val(x) native_pud_val(x)
109#define __pud(x) native_make_pud(x)
110#endif
111
112#ifndef __PAGETABLE_PMD_FOLDED
113#define pmd_val(x) native_pmd_val(x)
114#define __pmd(x) native_make_pmd(x)
115#endif
116
117#define pte_val(x) native_pte_val(x)
118#define __pte(x) native_make_pte(x)
119
120#define arch_end_context_switch(prev) do {} while(0)
121#endif /* CONFIG_PARAVIRT_XXL */
122
123static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set)
124{
125 pmdval_t v = native_pmd_val(pmd);
126
127 return native_make_pmd(val: v | set);
128}
129
130static inline pmd_t pmd_clear_flags(pmd_t pmd, pmdval_t clear)
131{
132 pmdval_t v = native_pmd_val(pmd);
133
134 return native_make_pmd(val: v & ~clear);
135}
136
137static inline pud_t pud_set_flags(pud_t pud, pudval_t set)
138{
139 pudval_t v = native_pud_val(pud);
140
141 return native_make_pud(val: v | set);
142}
143
144static inline pud_t pud_clear_flags(pud_t pud, pudval_t clear)
145{
146 pudval_t v = native_pud_val(pud);
147
148 return native_make_pud(val: v & ~clear);
149}
150
151/*
152 * The following only work if pte_present() is true.
153 * Undefined behaviour if not..
154 */
155static inline bool pte_dirty(pte_t pte)
156{
157 return pte_flags(pte) & _PAGE_DIRTY_BITS;
158}
159
160static inline bool pte_shstk(pte_t pte)
161{
162 return cpu_feature_enabled(X86_FEATURE_SHSTK) &&
163 (pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == _PAGE_DIRTY;
164}
165
166static inline int pte_young(pte_t pte)
167{
168 return pte_flags(pte) & _PAGE_ACCESSED;
169}
170
171static inline bool pte_decrypted(pte_t pte)
172{
173 return cc_mkdec(val: pte_val(pte)) == pte_val(pte);
174}
175
176#define pmd_dirty pmd_dirty
177static inline bool pmd_dirty(pmd_t pmd)
178{
179 return pmd_flags(pmd) & _PAGE_DIRTY_BITS;
180}
181
182static inline bool pmd_shstk(pmd_t pmd)
183{
184 return cpu_feature_enabled(X86_FEATURE_SHSTK) &&
185 (pmd_flags(pmd) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) ==
186 (_PAGE_DIRTY | _PAGE_PSE);
187}
188
189#define pmd_young pmd_young
190static inline int pmd_young(pmd_t pmd)
191{
192 return pmd_flags(pmd) & _PAGE_ACCESSED;
193}
194
195static inline bool pud_dirty(pud_t pud)
196{
197 return pud_flags(pud) & _PAGE_DIRTY_BITS;
198}
199
200static inline int pud_young(pud_t pud)
201{
202 return pud_flags(pud) & _PAGE_ACCESSED;
203}
204
205static inline bool pud_shstk(pud_t pud)
206{
207 return cpu_feature_enabled(X86_FEATURE_SHSTK) &&
208 (pud_flags(pud) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) ==
209 (_PAGE_DIRTY | _PAGE_PSE);
210}
211
212static inline int pte_write(pte_t pte)
213{
214 /*
215 * Shadow stack pages are logically writable, but do not have
216 * _PAGE_RW. Check for them separately from _PAGE_RW itself.
217 */
218 return (pte_flags(pte) & _PAGE_RW) || pte_shstk(pte);
219}
220
221#define pmd_write pmd_write
222static inline int pmd_write(pmd_t pmd)
223{
224 /*
225 * Shadow stack pages are logically writable, but do not have
226 * _PAGE_RW. Check for them separately from _PAGE_RW itself.
227 */
228 return (pmd_flags(pmd) & _PAGE_RW) || pmd_shstk(pmd);
229}
230
231#define pud_write pud_write
232static inline int pud_write(pud_t pud)
233{
234 return pud_flags(pud) & _PAGE_RW;
235}
236
237static inline int pte_huge(pte_t pte)
238{
239 return pte_flags(pte) & _PAGE_PSE;
240}
241
242static inline int pte_global(pte_t pte)
243{
244 return pte_flags(pte) & _PAGE_GLOBAL;
245}
246
247static inline int pte_exec(pte_t pte)
248{
249 return !(pte_flags(pte) & _PAGE_NX);
250}
251
252static inline int pte_special(pte_t pte)
253{
254 return pte_flags(pte) & _PAGE_SPECIAL;
255}
256
257/* Entries that were set to PROT_NONE are inverted */
258
259static inline u64 protnone_mask(u64 val);
260
261#define PFN_PTE_SHIFT PAGE_SHIFT
262
263static inline unsigned long pte_pfn(pte_t pte)
264{
265 phys_addr_t pfn = pte_val(pte);
266 pfn ^= protnone_mask(val: pfn);
267 return (pfn & PTE_PFN_MASK) >> PAGE_SHIFT;
268}
269
270static inline unsigned long pmd_pfn(pmd_t pmd)
271{
272 phys_addr_t pfn = pmd_val(pmd);
273 pfn ^= protnone_mask(val: pfn);
274 return (pfn & pmd_pfn_mask(pmd)) >> PAGE_SHIFT;
275}
276
277#define pud_pfn pud_pfn
278static inline unsigned long pud_pfn(pud_t pud)
279{
280 phys_addr_t pfn = pud_val(pud);
281 pfn ^= protnone_mask(val: pfn);
282 return (pfn & pud_pfn_mask(pud)) >> PAGE_SHIFT;
283}
284
285static inline unsigned long p4d_pfn(p4d_t p4d)
286{
287 return (p4d_val(p4d) & p4d_pfn_mask(p4d)) >> PAGE_SHIFT;
288}
289
290static inline unsigned long pgd_pfn(pgd_t pgd)
291{
292 return (pgd_val(pgd) & PTE_PFN_MASK) >> PAGE_SHIFT;
293}
294
295#define pte_page(pte) pfn_to_page(pte_pfn(pte))
296
297#define pmd_leaf pmd_leaf
298static inline bool pmd_leaf(pmd_t pte)
299{
300 return pmd_flags(pmd: pte) & _PAGE_PSE;
301}
302
303#ifdef CONFIG_TRANSPARENT_HUGEPAGE
304static inline int pmd_trans_huge(pmd_t pmd)
305{
306 return (pmd_val(pmd) & _PAGE_PSE) == _PAGE_PSE;
307}
308
309#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
310static inline int pud_trans_huge(pud_t pud)
311{
312 return (pud_val(pud) & _PAGE_PSE) == _PAGE_PSE;
313}
314#endif
315
316#define has_transparent_hugepage has_transparent_hugepage
317static inline int has_transparent_hugepage(void)
318{
319 return boot_cpu_has(X86_FEATURE_PSE);
320}
321
322#ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP
323static inline bool pmd_special(pmd_t pmd)
324{
325 return pmd_flags(pmd) & _PAGE_SPECIAL;
326}
327
328static inline pmd_t pmd_mkspecial(pmd_t pmd)
329{
330 return pmd_set_flags(pmd, _PAGE_SPECIAL);
331}
332#endif /* CONFIG_ARCH_SUPPORTS_PMD_PFNMAP */
333
334#ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP
335static inline bool pud_special(pud_t pud)
336{
337 return pud_flags(pud) & _PAGE_SPECIAL;
338}
339
340static inline pud_t pud_mkspecial(pud_t pud)
341{
342 return pud_set_flags(pud, _PAGE_SPECIAL);
343}
344#endif /* CONFIG_ARCH_SUPPORTS_PUD_PFNMAP */
345#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
346
347static inline pte_t pte_set_flags(pte_t pte, pteval_t set)
348{
349 pteval_t v = native_pte_val(pte);
350
351 return native_make_pte(val: v | set);
352}
353
354static inline pte_t pte_clear_flags(pte_t pte, pteval_t clear)
355{
356 pteval_t v = native_pte_val(pte);
357
358 return native_make_pte(val: v & ~clear);
359}
360
361/*
362 * Write protection operations can result in Dirty=1,Write=0 PTEs. But in the
363 * case of X86_FEATURE_USER_SHSTK, these PTEs denote shadow stack memory. So
364 * when creating dirty, write-protected memory, a software bit is used:
365 * _PAGE_BIT_SAVED_DIRTY. The following functions take a PTE and transition the
366 * Dirty bit to SavedDirty, and vice-vesra.
367 *
368 * This shifting is only done if needed. In the case of shifting
369 * Dirty->SavedDirty, the condition is if the PTE is Write=0. In the case of
370 * shifting SavedDirty->Dirty, the condition is Write=1.
371 */
372static inline pgprotval_t mksaveddirty_shift(pgprotval_t v)
373{
374 pgprotval_t cond = (~v >> _PAGE_BIT_RW) & 1;
375
376 v |= ((v >> _PAGE_BIT_DIRTY) & cond) << _PAGE_BIT_SAVED_DIRTY;
377 v &= ~(cond << _PAGE_BIT_DIRTY);
378
379 return v;
380}
381
382static inline pgprotval_t clear_saveddirty_shift(pgprotval_t v)
383{
384 pgprotval_t cond = (v >> _PAGE_BIT_RW) & 1;
385
386 v |= ((v >> _PAGE_BIT_SAVED_DIRTY) & cond) << _PAGE_BIT_DIRTY;
387 v &= ~(cond << _PAGE_BIT_SAVED_DIRTY);
388
389 return v;
390}
391
392static inline pte_t pte_mksaveddirty(pte_t pte)
393{
394 pteval_t v = native_pte_val(pte);
395
396 v = mksaveddirty_shift(v);
397 return native_make_pte(val: v);
398}
399
400static inline pte_t pte_clear_saveddirty(pte_t pte)
401{
402 pteval_t v = native_pte_val(pte);
403
404 v = clear_saveddirty_shift(v);
405 return native_make_pte(val: v);
406}
407
408static inline pte_t pte_wrprotect(pte_t pte)
409{
410 pte = pte_clear_flags(pte, _PAGE_RW);
411
412 /*
413 * Blindly clearing _PAGE_RW might accidentally create
414 * a shadow stack PTE (Write=0,Dirty=1). Move the hardware
415 * dirty value to the software bit, if present.
416 */
417 return pte_mksaveddirty(pte);
418}
419
420#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
421static inline int pte_uffd_wp(pte_t pte)
422{
423 return pte_flags(pte) & _PAGE_UFFD_WP;
424}
425
426static inline pte_t pte_mkuffd_wp(pte_t pte)
427{
428 return pte_wrprotect(pte: pte_set_flags(pte, _PAGE_UFFD_WP));
429}
430
431static inline pte_t pte_clear_uffd_wp(pte_t pte)
432{
433 return pte_clear_flags(pte, _PAGE_UFFD_WP);
434}
435#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
436
437static inline pte_t pte_mkclean(pte_t pte)
438{
439 return pte_clear_flags(pte, _PAGE_DIRTY_BITS);
440}
441
442static inline pte_t pte_mkold(pte_t pte)
443{
444 return pte_clear_flags(pte, _PAGE_ACCESSED);
445}
446
447static inline pte_t pte_mkexec(pte_t pte)
448{
449 return pte_clear_flags(pte, _PAGE_NX);
450}
451
452static inline pte_t pte_mkdirty(pte_t pte)
453{
454 pte = pte_set_flags(pte, _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
455
456 return pte_mksaveddirty(pte);
457}
458
459static inline pte_t pte_mkwrite_shstk(pte_t pte)
460{
461 pte = pte_clear_flags(pte, _PAGE_RW);
462
463 return pte_set_flags(pte, _PAGE_DIRTY);
464}
465
466static inline pte_t pte_mkyoung(pte_t pte)
467{
468 return pte_set_flags(pte, _PAGE_ACCESSED);
469}
470
471static inline pte_t pte_mkwrite_novma(pte_t pte)
472{
473 return pte_set_flags(pte, _PAGE_RW);
474}
475
476struct vm_area_struct;
477pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma);
478#define pte_mkwrite pte_mkwrite
479
480static inline pte_t pte_mkhuge(pte_t pte)
481{
482 return pte_set_flags(pte, _PAGE_PSE);
483}
484
485static inline pte_t pte_clrhuge(pte_t pte)
486{
487 return pte_clear_flags(pte, _PAGE_PSE);
488}
489
490static inline pte_t pte_mkglobal(pte_t pte)
491{
492 return pte_set_flags(pte, _PAGE_GLOBAL);
493}
494
495static inline pte_t pte_clrglobal(pte_t pte)
496{
497 return pte_clear_flags(pte, _PAGE_GLOBAL);
498}
499
500static inline pte_t pte_mkspecial(pte_t pte)
501{
502 return pte_set_flags(pte, _PAGE_SPECIAL);
503}
504
505/* See comments above mksaveddirty_shift() */
506static inline pmd_t pmd_mksaveddirty(pmd_t pmd)
507{
508 pmdval_t v = native_pmd_val(pmd);
509
510 v = mksaveddirty_shift(v);
511 return native_make_pmd(val: v);
512}
513
514/* See comments above mksaveddirty_shift() */
515static inline pmd_t pmd_clear_saveddirty(pmd_t pmd)
516{
517 pmdval_t v = native_pmd_val(pmd);
518
519 v = clear_saveddirty_shift(v);
520 return native_make_pmd(val: v);
521}
522
523static inline pmd_t pmd_wrprotect(pmd_t pmd)
524{
525 pmd = pmd_clear_flags(pmd, _PAGE_RW);
526
527 /*
528 * Blindly clearing _PAGE_RW might accidentally create
529 * a shadow stack PMD (RW=0, Dirty=1). Move the hardware
530 * dirty value to the software bit.
531 */
532 return pmd_mksaveddirty(pmd);
533}
534
535#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
536static inline int pmd_uffd_wp(pmd_t pmd)
537{
538 return pmd_flags(pmd) & _PAGE_UFFD_WP;
539}
540
541static inline pmd_t pmd_mkuffd_wp(pmd_t pmd)
542{
543 return pmd_wrprotect(pmd: pmd_set_flags(pmd, _PAGE_UFFD_WP));
544}
545
546static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd)
547{
548 return pmd_clear_flags(pmd, _PAGE_UFFD_WP);
549}
550#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
551
552static inline pmd_t pmd_mkold(pmd_t pmd)
553{
554 return pmd_clear_flags(pmd, _PAGE_ACCESSED);
555}
556
557static inline pmd_t pmd_mkclean(pmd_t pmd)
558{
559 return pmd_clear_flags(pmd, _PAGE_DIRTY_BITS);
560}
561
562static inline pmd_t pmd_mkdirty(pmd_t pmd)
563{
564 pmd = pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
565
566 return pmd_mksaveddirty(pmd);
567}
568
569static inline pmd_t pmd_mkwrite_shstk(pmd_t pmd)
570{
571 pmd = pmd_clear_flags(pmd, _PAGE_RW);
572
573 return pmd_set_flags(pmd, _PAGE_DIRTY);
574}
575
576static inline pmd_t pmd_mkhuge(pmd_t pmd)
577{
578 return pmd_set_flags(pmd, _PAGE_PSE);
579}
580
581static inline pmd_t pmd_mkyoung(pmd_t pmd)
582{
583 return pmd_set_flags(pmd, _PAGE_ACCESSED);
584}
585
586static inline pmd_t pmd_mkwrite_novma(pmd_t pmd)
587{
588 return pmd_set_flags(pmd, _PAGE_RW);
589}
590
591pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma);
592#define pmd_mkwrite pmd_mkwrite
593
594/* See comments above mksaveddirty_shift() */
595static inline pud_t pud_mksaveddirty(pud_t pud)
596{
597 pudval_t v = native_pud_val(pud);
598
599 v = mksaveddirty_shift(v);
600 return native_make_pud(val: v);
601}
602
603/* See comments above mksaveddirty_shift() */
604static inline pud_t pud_clear_saveddirty(pud_t pud)
605{
606 pudval_t v = native_pud_val(pud);
607
608 v = clear_saveddirty_shift(v);
609 return native_make_pud(val: v);
610}
611
612static inline pud_t pud_mkold(pud_t pud)
613{
614 return pud_clear_flags(pud, _PAGE_ACCESSED);
615}
616
617static inline pud_t pud_mkclean(pud_t pud)
618{
619 return pud_clear_flags(pud, _PAGE_DIRTY_BITS);
620}
621
622static inline pud_t pud_wrprotect(pud_t pud)
623{
624 pud = pud_clear_flags(pud, _PAGE_RW);
625
626 /*
627 * Blindly clearing _PAGE_RW might accidentally create
628 * a shadow stack PUD (RW=0, Dirty=1). Move the hardware
629 * dirty value to the software bit.
630 */
631 return pud_mksaveddirty(pud);
632}
633
634static inline pud_t pud_mkdirty(pud_t pud)
635{
636 pud = pud_set_flags(pud, _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
637
638 return pud_mksaveddirty(pud);
639}
640
641static inline pud_t pud_mkhuge(pud_t pud)
642{
643 return pud_set_flags(pud, _PAGE_PSE);
644}
645
646static inline pud_t pud_mkyoung(pud_t pud)
647{
648 return pud_set_flags(pud, _PAGE_ACCESSED);
649}
650
651static inline pud_t pud_mkwrite(pud_t pud)
652{
653 pud = pud_set_flags(pud, _PAGE_RW);
654
655 return pud_clear_saveddirty(pud);
656}
657
658#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
659static inline int pte_soft_dirty(pte_t pte)
660{
661 return pte_flags(pte) & _PAGE_SOFT_DIRTY;
662}
663
664static inline int pmd_soft_dirty(pmd_t pmd)
665{
666 return pmd_flags(pmd) & _PAGE_SOFT_DIRTY;
667}
668
669static inline int pud_soft_dirty(pud_t pud)
670{
671 return pud_flags(pud) & _PAGE_SOFT_DIRTY;
672}
673
674static inline pte_t pte_mksoft_dirty(pte_t pte)
675{
676 return pte_set_flags(pte, _PAGE_SOFT_DIRTY);
677}
678
679static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
680{
681 return pmd_set_flags(pmd, _PAGE_SOFT_DIRTY);
682}
683
684static inline pud_t pud_mksoft_dirty(pud_t pud)
685{
686 return pud_set_flags(pud, _PAGE_SOFT_DIRTY);
687}
688
689static inline pte_t pte_clear_soft_dirty(pte_t pte)
690{
691 return pte_clear_flags(pte, _PAGE_SOFT_DIRTY);
692}
693
694static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
695{
696 return pmd_clear_flags(pmd, _PAGE_SOFT_DIRTY);
697}
698
699static inline pud_t pud_clear_soft_dirty(pud_t pud)
700{
701 return pud_clear_flags(pud, _PAGE_SOFT_DIRTY);
702}
703
704#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
705
706/*
707 * Mask out unsupported bits in a present pgprot. Non-present pgprots
708 * can use those bits for other purposes, so leave them be.
709 */
710static inline pgprotval_t massage_pgprot(pgprot_t pgprot)
711{
712 pgprotval_t protval = pgprot_val(pgprot);
713
714 if (protval & _PAGE_PRESENT)
715 protval &= __supported_pte_mask;
716
717 return protval;
718}
719
720static inline pgprotval_t check_pgprot(pgprot_t pgprot)
721{
722 pgprotval_t massaged_val = massage_pgprot(pgprot);
723
724 /* mmdebug.h can not be included here because of dependencies */
725#ifdef CONFIG_DEBUG_VM
726 WARN_ONCE(pgprot_val(pgprot) != massaged_val,
727 "attempted to set unsupported pgprot: %016llx "
728 "bits: %016llx supported: %016llx\n",
729 (u64)pgprot_val(pgprot),
730 (u64)pgprot_val(pgprot) ^ massaged_val,
731 (u64)__supported_pte_mask);
732#endif
733
734 return massaged_val;
735}
736
737static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
738{
739 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT;
740 /* This bit combination is used to mark shadow stacks */
741 WARN_ON_ONCE((pgprot_val(pgprot) & (_PAGE_DIRTY | _PAGE_RW)) ==
742 _PAGE_DIRTY);
743 pfn ^= protnone_mask(pgprot_val(pgprot));
744 pfn &= PTE_PFN_MASK;
745 return __pte(val: pfn | check_pgprot(pgprot));
746}
747
748static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
749{
750 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT;
751 pfn ^= protnone_mask(pgprot_val(pgprot));
752 pfn &= PHYSICAL_PMD_PAGE_MASK;
753 return __pmd(val: pfn | check_pgprot(pgprot));
754}
755
756static inline pud_t pfn_pud(unsigned long page_nr, pgprot_t pgprot)
757{
758 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT;
759 pfn ^= protnone_mask(pgprot_val(pgprot));
760 pfn &= PHYSICAL_PUD_PAGE_MASK;
761 return __pud(val: pfn | check_pgprot(pgprot));
762}
763
764static inline pmd_t pmd_mkinvalid(pmd_t pmd)
765{
766 return pfn_pmd(page_nr: pmd_pfn(pmd),
767 __pgprot(pmd_flags(pmd) & ~(_PAGE_PRESENT|_PAGE_PROTNONE)));
768}
769
770static inline pud_t pud_mkinvalid(pud_t pud)
771{
772 return pfn_pud(pud_pfn(pud),
773 __pgprot(pud_flags(pud) & ~(_PAGE_PRESENT|_PAGE_PROTNONE)));
774}
775
776static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask);
777
778static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
779{
780 pteval_t val = pte_val(pte), oldval = val;
781 pte_t pte_result;
782
783 /*
784 * Chop off the NX bit (if present), and add the NX portion of
785 * the newprot (if present):
786 */
787 val &= _PAGE_CHG_MASK;
788 val |= check_pgprot(pgprot: newprot) & ~_PAGE_CHG_MASK;
789 val = flip_protnone_guard(oldval, val, PTE_PFN_MASK);
790
791 pte_result = __pte(val);
792
793 /*
794 * To avoid creating Write=0,Dirty=1 PTEs, pte_modify() needs to avoid:
795 * 1. Marking Write=0 PTEs Dirty=1
796 * 2. Marking Dirty=1 PTEs Write=0
797 *
798 * The first case cannot happen because the _PAGE_CHG_MASK will filter
799 * out any Dirty bit passed in newprot. Handle the second case by
800 * going through the mksaveddirty exercise. Only do this if the old
801 * value was Write=1 to avoid doing this on Shadow Stack PTEs.
802 */
803 if (oldval & _PAGE_RW)
804 pte_result = pte_mksaveddirty(pte: pte_result);
805 else
806 pte_result = pte_clear_saveddirty(pte: pte_result);
807
808 return pte_result;
809}
810
811static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
812{
813 pmdval_t val = pmd_val(pmd), oldval = val;
814 pmd_t pmd_result;
815
816 val &= (_HPAGE_CHG_MASK & ~_PAGE_DIRTY);
817 val |= check_pgprot(pgprot: newprot) & ~_HPAGE_CHG_MASK;
818 val = flip_protnone_guard(oldval, val, PHYSICAL_PMD_PAGE_MASK);
819
820 pmd_result = __pmd(val);
821
822 /*
823 * Avoid creating shadow stack PMD by accident. See comment in
824 * pte_modify().
825 */
826 if (oldval & _PAGE_RW)
827 pmd_result = pmd_mksaveddirty(pmd: pmd_result);
828 else
829 pmd_result = pmd_clear_saveddirty(pmd: pmd_result);
830
831 return pmd_result;
832}
833
834static inline pud_t pud_modify(pud_t pud, pgprot_t newprot)
835{
836 pudval_t val = pud_val(pud), oldval = val;
837 pud_t pud_result;
838
839 val &= _HPAGE_CHG_MASK;
840 val |= check_pgprot(pgprot: newprot) & ~_HPAGE_CHG_MASK;
841 val = flip_protnone_guard(oldval, val, PHYSICAL_PUD_PAGE_MASK);
842
843 pud_result = __pud(val);
844
845 /*
846 * Avoid creating shadow stack PUD by accident. See comment in
847 * pte_modify().
848 */
849 if (oldval & _PAGE_RW)
850 pud_result = pud_mksaveddirty(pud: pud_result);
851 else
852 pud_result = pud_clear_saveddirty(pud: pud_result);
853
854 return pud_result;
855}
856
857/*
858 * mprotect needs to preserve PAT and encryption bits when updating
859 * vm_page_prot
860 */
861#define pgprot_modify pgprot_modify
862static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
863{
864 pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK;
865 pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK;
866 return __pgprot(preservebits | addbits);
867}
868
869#define pte_pgprot(x) __pgprot(pte_flags(x))
870#define pmd_pgprot(x) __pgprot(pmd_flags(x))
871#define pud_pgprot(x) __pgprot(pud_flags(x))
872#define p4d_pgprot(x) __pgprot(p4d_flags(x))
873
874#define canon_pgprot(p) __pgprot(massage_pgprot(p))
875
876static inline int is_new_memtype_allowed(u64 paddr, unsigned long size,
877 enum page_cache_mode pcm,
878 enum page_cache_mode new_pcm)
879{
880 /*
881 * PAT type is always WB for untracked ranges, so no need to check.
882 */
883 if (x86_platform.is_untracked_pat_range(paddr, paddr + size))
884 return 1;
885
886 /*
887 * Certain new memtypes are not allowed with certain
888 * requested memtype:
889 * - request is uncached, return cannot be write-back
890 * - request is write-combine, return cannot be write-back
891 * - request is write-through, return cannot be write-back
892 * - request is write-through, return cannot be write-combine
893 */
894 if ((pcm == _PAGE_CACHE_MODE_UC_MINUS &&
895 new_pcm == _PAGE_CACHE_MODE_WB) ||
896 (pcm == _PAGE_CACHE_MODE_WC &&
897 new_pcm == _PAGE_CACHE_MODE_WB) ||
898 (pcm == _PAGE_CACHE_MODE_WT &&
899 new_pcm == _PAGE_CACHE_MODE_WB) ||
900 (pcm == _PAGE_CACHE_MODE_WT &&
901 new_pcm == _PAGE_CACHE_MODE_WC)) {
902 return 0;
903 }
904
905 return 1;
906}
907
908pmd_t *populate_extra_pmd(unsigned long vaddr);
909pte_t *populate_extra_pte(unsigned long vaddr);
910
911#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
912pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd);
913
914/*
915 * Take a PGD location (pgdp) and a pgd value that needs to be set there.
916 * Populates the user and returns the resulting PGD that must be set in
917 * the kernel copy of the page tables.
918 */
919static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd)
920{
921 if (!static_cpu_has(X86_FEATURE_PTI))
922 return pgd;
923 return __pti_set_user_pgtbl(pgdp, pgd);
924}
925#else /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */
926static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd)
927{
928 return pgd;
929}
930#endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */
931
932#endif /* __ASSEMBLER__ */
933
934
935#ifdef CONFIG_X86_32
936# include <asm/pgtable_32.h>
937#else
938# include <asm/pgtable_64.h>
939#endif
940
941#ifndef __ASSEMBLER__
942#include <linux/mm_types.h>
943#include <linux/mmdebug.h>
944#include <linux/log2.h>
945#include <asm/fixmap.h>
946
947static inline int pte_none(pte_t pte)
948{
949 return !(pte.pte & ~(_PAGE_KNL_ERRATUM_MASK));
950}
951
952#define __HAVE_ARCH_PTE_SAME
953static inline int pte_same(pte_t a, pte_t b)
954{
955 return a.pte == b.pte;
956}
957
958static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr)
959{
960 if (__pte_needs_invert(val: pte_val(pte)))
961 return __pte(val: pte_val(pte) - (nr << PFN_PTE_SHIFT));
962 return __pte(val: pte_val(pte) + (nr << PFN_PTE_SHIFT));
963}
964#define pte_advance_pfn pte_advance_pfn
965
966static inline int pte_present(pte_t a)
967{
968 return pte_flags(pte: a) & (_PAGE_PRESENT | _PAGE_PROTNONE);
969}
970
971#define pte_accessible pte_accessible
972static inline bool pte_accessible(struct mm_struct *mm, pte_t a)
973{
974 if (pte_flags(pte: a) & _PAGE_PRESENT)
975 return true;
976
977 if ((pte_flags(pte: a) & _PAGE_PROTNONE) &&
978 atomic_read(v: &mm->tlb_flush_pending))
979 return true;
980
981 return false;
982}
983
984static inline int pmd_present(pmd_t pmd)
985{
986 /*
987 * Checking for _PAGE_PSE is needed too because
988 * split_huge_page will temporarily clear the present bit (but
989 * the _PAGE_PSE flag will remain set at all times while the
990 * _PAGE_PRESENT bit is clear).
991 */
992 return pmd_flags(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PSE);
993}
994
995#ifdef CONFIG_NUMA_BALANCING
996/*
997 * These work without NUMA balancing but the kernel does not care. See the
998 * comment in include/linux/pgtable.h
999 */
1000static inline int pte_protnone(pte_t pte)
1001{
1002 return (pte_flags(pte) & (_PAGE_PROTNONE | _PAGE_PRESENT))
1003 == _PAGE_PROTNONE;
1004}
1005
1006static inline int pmd_protnone(pmd_t pmd)
1007{
1008 return (pmd_flags(pmd) & (_PAGE_PROTNONE | _PAGE_PRESENT))
1009 == _PAGE_PROTNONE;
1010}
1011#endif /* CONFIG_NUMA_BALANCING */
1012
1013static inline int pmd_none(pmd_t pmd)
1014{
1015 /* Only check low word on 32-bit platforms, since it might be
1016 out of sync with upper half. */
1017 unsigned long val = native_pmd_val(pmd);
1018 return (val & ~_PAGE_KNL_ERRATUM_MASK) == 0;
1019}
1020
1021static inline unsigned long pmd_page_vaddr(pmd_t pmd)
1022{
1023 return (unsigned long)__va(pmd_val(pmd) & pmd_pfn_mask(pmd));
1024}
1025
1026/*
1027 * Currently stuck as a macro due to indirect forward reference to
1028 * linux/mmzone.h's __section_mem_map_addr() definition:
1029 */
1030#define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd))
1031
1032static inline int pmd_bad(pmd_t pmd)
1033{
1034 return (pmd_flags(pmd) & ~(_PAGE_USER | _PAGE_ACCESSED)) !=
1035 (_KERNPG_TABLE & ~_PAGE_ACCESSED);
1036}
1037
1038static inline unsigned long pages_to_mb(unsigned long npg)
1039{
1040 return npg >> (20 - PAGE_SHIFT);
1041}
1042
1043#if CONFIG_PGTABLE_LEVELS > 2
1044static inline int pud_none(pud_t pud)
1045{
1046 return (native_pud_val(pud) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0;
1047}
1048
1049static inline int pud_present(pud_t pud)
1050{
1051 return pud_flags(pud) & _PAGE_PRESENT;
1052}
1053
1054static inline pmd_t *pud_pgtable(pud_t pud)
1055{
1056 return (pmd_t *)__va(pud_val(pud) & pud_pfn_mask(pud));
1057}
1058
1059/*
1060 * Currently stuck as a macro due to indirect forward reference to
1061 * linux/mmzone.h's __section_mem_map_addr() definition:
1062 */
1063#define pud_page(pud) pfn_to_page(pud_pfn(pud))
1064
1065#define pud_leaf pud_leaf
1066static inline bool pud_leaf(pud_t pud)
1067{
1068 return pud_val(pud) & _PAGE_PSE;
1069}
1070
1071static inline int pud_bad(pud_t pud)
1072{
1073 return (pud_flags(pud) & ~(_KERNPG_TABLE | _PAGE_USER)) != 0;
1074}
1075#endif /* CONFIG_PGTABLE_LEVELS > 2 */
1076
1077#if CONFIG_PGTABLE_LEVELS > 3
1078static inline int p4d_none(p4d_t p4d)
1079{
1080 return (native_p4d_val(p4d) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0;
1081}
1082
1083static inline int p4d_present(p4d_t p4d)
1084{
1085 return p4d_flags(p4d) & _PAGE_PRESENT;
1086}
1087
1088static inline pud_t *p4d_pgtable(p4d_t p4d)
1089{
1090 return (pud_t *)__va(p4d_val(p4d) & p4d_pfn_mask(p4d));
1091}
1092
1093/*
1094 * Currently stuck as a macro due to indirect forward reference to
1095 * linux/mmzone.h's __section_mem_map_addr() definition:
1096 */
1097#define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d))
1098
1099static inline int p4d_bad(p4d_t p4d)
1100{
1101 unsigned long ignore_flags = _KERNPG_TABLE | _PAGE_USER;
1102
1103 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION))
1104 ignore_flags |= _PAGE_NX;
1105
1106 return (p4d_flags(p4d) & ~ignore_flags) != 0;
1107}
1108#endif /* CONFIG_PGTABLE_LEVELS > 3 */
1109
1110static inline unsigned long p4d_index(unsigned long address)
1111{
1112 return (address >> P4D_SHIFT) & (PTRS_PER_P4D - 1);
1113}
1114
1115#if CONFIG_PGTABLE_LEVELS > 4
1116static inline int pgd_present(pgd_t pgd)
1117{
1118 if (!pgtable_l5_enabled())
1119 return 1;
1120 return pgd_flags(pgd) & _PAGE_PRESENT;
1121}
1122
1123static inline unsigned long pgd_page_vaddr(pgd_t pgd)
1124{
1125 return (unsigned long)__va((unsigned long)pgd_val(pgd) & PTE_PFN_MASK);
1126}
1127
1128/*
1129 * Currently stuck as a macro due to indirect forward reference to
1130 * linux/mmzone.h's __section_mem_map_addr() definition:
1131 */
1132#define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd))
1133
1134/* to find an entry in a page-table-directory. */
1135static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address)
1136{
1137 if (!pgtable_l5_enabled())
1138 return (p4d_t *)pgd;
1139 return (p4d_t *)pgd_page_vaddr(pgd: *pgd) + p4d_index(address);
1140}
1141
1142static inline int pgd_bad(pgd_t pgd)
1143{
1144 unsigned long ignore_flags = _PAGE_USER;
1145
1146 if (!pgtable_l5_enabled())
1147 return 0;
1148
1149 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION))
1150 ignore_flags |= _PAGE_NX;
1151
1152 return (pgd_flags(pgd) & ~ignore_flags) != _KERNPG_TABLE;
1153}
1154
1155static inline int pgd_none(pgd_t pgd)
1156{
1157 if (!pgtable_l5_enabled())
1158 return 0;
1159 /*
1160 * There is no need to do a workaround for the KNL stray
1161 * A/D bit erratum here. PGDs only point to page tables
1162 * except on 32-bit non-PAE which is not supported on
1163 * KNL.
1164 */
1165 return !native_pgd_val(pgd);
1166}
1167#endif /* CONFIG_PGTABLE_LEVELS > 4 */
1168
1169#endif /* __ASSEMBLER__ */
1170
1171#define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET)
1172#define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY)
1173
1174#ifndef __ASSEMBLER__
1175
1176extern int direct_gbpages;
1177void init_mem_mapping(void);
1178void early_alloc_pgt_buf(void);
1179void __init poking_init(void);
1180unsigned long init_memory_mapping(unsigned long start,
1181 unsigned long end, pgprot_t prot);
1182
1183#ifdef CONFIG_X86_64
1184extern pgd_t trampoline_pgd_entry;
1185#endif
1186
1187/* local pte updates need not use xchg for locking */
1188static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep)
1189{
1190 pte_t res = *ptep;
1191
1192 /* Pure native function needs no input for mm, addr */
1193 native_pte_clear(NULL, addr: 0, ptep);
1194 return res;
1195}
1196
1197static inline pmd_t native_local_pmdp_get_and_clear(pmd_t *pmdp)
1198{
1199 pmd_t res = *pmdp;
1200
1201 native_pmd_clear(pmd: pmdp);
1202 return res;
1203}
1204
1205static inline pud_t native_local_pudp_get_and_clear(pud_t *pudp)
1206{
1207 pud_t res = *pudp;
1208
1209 native_pud_clear(pud: pudp);
1210 return res;
1211}
1212
1213static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1214 pmd_t *pmdp, pmd_t pmd)
1215{
1216 page_table_check_pmd_set(mm, pmdp, pmd);
1217 set_pmd(pmdp, pmd);
1218}
1219
1220static inline void set_pud_at(struct mm_struct *mm, unsigned long addr,
1221 pud_t *pudp, pud_t pud)
1222{
1223 page_table_check_pud_set(mm, pudp, pud);
1224 native_set_pud(pudp, pud);
1225}
1226
1227/*
1228 * We only update the dirty/accessed state if we set
1229 * the dirty bit by hand in the kernel, since the hardware
1230 * will do the accessed bit for us, and we don't want to
1231 * race with other CPU's that might be updating the dirty
1232 * bit at the same time.
1233 */
1234struct vm_area_struct;
1235
1236#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1237extern int ptep_set_access_flags(struct vm_area_struct *vma,
1238 unsigned long address, pte_t *ptep,
1239 pte_t entry, int dirty);
1240
1241#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1242extern int ptep_test_and_clear_young(struct vm_area_struct *vma,
1243 unsigned long addr, pte_t *ptep);
1244
1245#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1246extern int ptep_clear_flush_young(struct vm_area_struct *vma,
1247 unsigned long address, pte_t *ptep);
1248
1249#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1250static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
1251 pte_t *ptep)
1252{
1253 pte_t pte = native_ptep_get_and_clear(xp: ptep);
1254 page_table_check_pte_clear(mm, pte);
1255 return pte;
1256}
1257
1258#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1259static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
1260 unsigned long addr, pte_t *ptep,
1261 int full)
1262{
1263 pte_t pte;
1264 if (full) {
1265 /*
1266 * Full address destruction in progress; paravirt does not
1267 * care about updates and native needs no locking
1268 */
1269 pte = native_local_ptep_get_and_clear(ptep);
1270 page_table_check_pte_clear(mm, pte);
1271 } else {
1272 pte = ptep_get_and_clear(mm, addr, ptep);
1273 }
1274 return pte;
1275}
1276
1277#define __HAVE_ARCH_PTEP_SET_WRPROTECT
1278static inline void ptep_set_wrprotect(struct mm_struct *mm,
1279 unsigned long addr, pte_t *ptep)
1280{
1281 /*
1282 * Avoid accidentally creating shadow stack PTEs
1283 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with
1284 * the hardware setting Dirty=1.
1285 */
1286 pte_t old_pte, new_pte;
1287
1288 old_pte = READ_ONCE(*ptep);
1289 do {
1290 new_pte = pte_wrprotect(pte: old_pte);
1291 } while (!try_cmpxchg((long *)&ptep->pte, (long *)&old_pte, *(long *)&new_pte));
1292}
1293
1294#define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0)
1295
1296#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1297extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1298 unsigned long address, pmd_t *pmdp,
1299 pmd_t entry, int dirty);
1300extern int pudp_set_access_flags(struct vm_area_struct *vma,
1301 unsigned long address, pud_t *pudp,
1302 pud_t entry, int dirty);
1303
1304#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1305extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1306 unsigned long addr, pmd_t *pmdp);
1307extern int pudp_test_and_clear_young(struct vm_area_struct *vma,
1308 unsigned long addr, pud_t *pudp);
1309
1310#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
1311extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
1312 unsigned long address, pmd_t *pmdp);
1313
1314
1315#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1316static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, unsigned long addr,
1317 pmd_t *pmdp)
1318{
1319 pmd_t pmd = native_pmdp_get_and_clear(xp: pmdp);
1320
1321 page_table_check_pmd_clear(mm, pmd);
1322
1323 return pmd;
1324}
1325
1326#define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
1327static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
1328 unsigned long addr, pud_t *pudp)
1329{
1330 pud_t pud = native_pudp_get_and_clear(xp: pudp);
1331
1332 page_table_check_pud_clear(mm, pud);
1333
1334 return pud;
1335}
1336
1337#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1338static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1339 unsigned long addr, pmd_t *pmdp)
1340{
1341 /*
1342 * Avoid accidentally creating shadow stack PTEs
1343 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with
1344 * the hardware setting Dirty=1.
1345 */
1346 pmd_t old_pmd, new_pmd;
1347
1348 old_pmd = READ_ONCE(*pmdp);
1349 do {
1350 new_pmd = pmd_wrprotect(pmd: old_pmd);
1351 } while (!try_cmpxchg((long *)pmdp, (long *)&old_pmd, *(long *)&new_pmd));
1352}
1353
1354#ifndef pmdp_establish
1355#define pmdp_establish pmdp_establish
1356static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
1357 unsigned long address, pmd_t *pmdp, pmd_t pmd)
1358{
1359 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd);
1360 if (IS_ENABLED(CONFIG_SMP)) {
1361 return xchg(pmdp, pmd);
1362 } else {
1363 pmd_t old = *pmdp;
1364 WRITE_ONCE(*pmdp, pmd);
1365 return old;
1366 }
1367}
1368#endif
1369
1370#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
1371static inline pud_t pudp_establish(struct vm_area_struct *vma,
1372 unsigned long address, pud_t *pudp, pud_t pud)
1373{
1374 page_table_check_pud_set(vma->vm_mm, pudp, pud);
1375 if (IS_ENABLED(CONFIG_SMP)) {
1376 return xchg(pudp, pud);
1377 } else {
1378 pud_t old = *pudp;
1379 WRITE_ONCE(*pudp, pud);
1380 return old;
1381 }
1382}
1383#endif
1384
1385#define __HAVE_ARCH_PMDP_INVALIDATE_AD
1386extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma,
1387 unsigned long address, pmd_t *pmdp);
1388
1389pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address,
1390 pud_t *pudp);
1391
1392/*
1393 * Page table pages are page-aligned. The lower half of the top
1394 * level is used for userspace and the top half for the kernel.
1395 *
1396 * Returns true for parts of the PGD that map userspace and
1397 * false for the parts that map the kernel.
1398 */
1399static inline bool pgdp_maps_userspace(void *__ptr)
1400{
1401 unsigned long ptr = (unsigned long)__ptr;
1402
1403 return (((ptr & ~PAGE_MASK) / sizeof(pgd_t)) < PGD_KERNEL_START);
1404}
1405
1406#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
1407/*
1408 * All top-level MITIGATION_PAGE_TABLE_ISOLATION page tables are order-1 pages
1409 * (8k-aligned and 8k in size). The kernel one is at the beginning 4k and
1410 * the user one is in the last 4k. To switch between them, you
1411 * just need to flip the 12th bit in their addresses.
1412 */
1413#define PTI_PGTABLE_SWITCH_BIT PAGE_SHIFT
1414
1415/*
1416 * This generates better code than the inline assembly in
1417 * __set_bit().
1418 */
1419static inline void *ptr_set_bit(void *ptr, int bit)
1420{
1421 unsigned long __ptr = (unsigned long)ptr;
1422
1423 __ptr |= BIT(bit);
1424 return (void *)__ptr;
1425}
1426static inline void *ptr_clear_bit(void *ptr, int bit)
1427{
1428 unsigned long __ptr = (unsigned long)ptr;
1429
1430 __ptr &= ~BIT(bit);
1431 return (void *)__ptr;
1432}
1433
1434static inline pgd_t *kernel_to_user_pgdp(pgd_t *pgdp)
1435{
1436 return ptr_set_bit(ptr: pgdp, PTI_PGTABLE_SWITCH_BIT);
1437}
1438
1439static inline pgd_t *user_to_kernel_pgdp(pgd_t *pgdp)
1440{
1441 return ptr_clear_bit(ptr: pgdp, PTI_PGTABLE_SWITCH_BIT);
1442}
1443
1444static inline p4d_t *kernel_to_user_p4dp(p4d_t *p4dp)
1445{
1446 return ptr_set_bit(ptr: p4dp, PTI_PGTABLE_SWITCH_BIT);
1447}
1448
1449static inline p4d_t *user_to_kernel_p4dp(p4d_t *p4dp)
1450{
1451 return ptr_clear_bit(ptr: p4dp, PTI_PGTABLE_SWITCH_BIT);
1452}
1453#endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */
1454
1455/*
1456 * clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
1457 *
1458 * dst - pointer to pgd range anywhere on a pgd page
1459 * src - ""
1460 * count - the number of pgds to copy.
1461 *
1462 * dst and src can be on the same page, but the range must not overlap,
1463 * and must not cross a page boundary.
1464 */
1465static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
1466{
1467 memcpy(dst, src, count * sizeof(pgd_t));
1468#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
1469 if (!static_cpu_has(X86_FEATURE_PTI))
1470 return;
1471 /* Clone the user space pgd as well */
1472 memcpy(kernel_to_user_pgdp(dst), kernel_to_user_pgdp(src),
1473 count * sizeof(pgd_t));
1474#endif
1475}
1476
1477#define PTE_SHIFT ilog2(PTRS_PER_PTE)
1478static inline int page_level_shift(enum pg_level level)
1479{
1480 return (PAGE_SHIFT - PTE_SHIFT) + level * PTE_SHIFT;
1481}
1482static inline unsigned long page_level_size(enum pg_level level)
1483{
1484 return 1UL << page_level_shift(level);
1485}
1486static inline unsigned long page_level_mask(enum pg_level level)
1487{
1488 return ~(page_level_size(level) - 1);
1489}
1490
1491/*
1492 * The x86 doesn't have any external MMU info: the kernel page
1493 * tables contain all the necessary information.
1494 */
1495static inline void update_mmu_cache(struct vm_area_struct *vma,
1496 unsigned long addr, pte_t *ptep)
1497{
1498}
1499static inline void update_mmu_cache_range(struct vm_fault *vmf,
1500 struct vm_area_struct *vma, unsigned long addr,
1501 pte_t *ptep, unsigned int nr)
1502{
1503}
1504static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
1505 unsigned long addr, pmd_t *pmd)
1506{
1507}
1508static inline void update_mmu_cache_pud(struct vm_area_struct *vma,
1509 unsigned long addr, pud_t *pud)
1510{
1511}
1512static inline pte_t pte_swp_mkexclusive(pte_t pte)
1513{
1514 return pte_set_flags(pte, _PAGE_SWP_EXCLUSIVE);
1515}
1516
1517static inline bool pte_swp_exclusive(pte_t pte)
1518{
1519 return pte_flags(pte) & _PAGE_SWP_EXCLUSIVE;
1520}
1521
1522static inline pte_t pte_swp_clear_exclusive(pte_t pte)
1523{
1524 return pte_clear_flags(pte, _PAGE_SWP_EXCLUSIVE);
1525}
1526
1527#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1528static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
1529{
1530 return pte_set_flags(pte, _PAGE_SWP_SOFT_DIRTY);
1531}
1532
1533static inline int pte_swp_soft_dirty(pte_t pte)
1534{
1535 return pte_flags(pte) & _PAGE_SWP_SOFT_DIRTY;
1536}
1537
1538static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
1539{
1540 return pte_clear_flags(pte, _PAGE_SWP_SOFT_DIRTY);
1541}
1542
1543#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
1544static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
1545{
1546 return pmd_set_flags(pmd, _PAGE_SWP_SOFT_DIRTY);
1547}
1548
1549static inline int pmd_swp_soft_dirty(pmd_t pmd)
1550{
1551 return pmd_flags(pmd) & _PAGE_SWP_SOFT_DIRTY;
1552}
1553
1554static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
1555{
1556 return pmd_clear_flags(pmd, _PAGE_SWP_SOFT_DIRTY);
1557}
1558#endif
1559#endif
1560
1561#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
1562static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
1563{
1564 return pte_set_flags(pte, _PAGE_SWP_UFFD_WP);
1565}
1566
1567static inline int pte_swp_uffd_wp(pte_t pte)
1568{
1569 return pte_flags(pte) & _PAGE_SWP_UFFD_WP;
1570}
1571
1572static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
1573{
1574 return pte_clear_flags(pte, _PAGE_SWP_UFFD_WP);
1575}
1576
1577static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd)
1578{
1579 return pmd_set_flags(pmd, _PAGE_SWP_UFFD_WP);
1580}
1581
1582static inline int pmd_swp_uffd_wp(pmd_t pmd)
1583{
1584 return pmd_flags(pmd) & _PAGE_SWP_UFFD_WP;
1585}
1586
1587static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd)
1588{
1589 return pmd_clear_flags(pmd, _PAGE_SWP_UFFD_WP);
1590}
1591#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
1592
1593static inline u16 pte_flags_pkey(unsigned long pte_flags)
1594{
1595#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1596 /* ifdef to avoid doing 59-bit shift on 32-bit values */
1597 return (pte_flags & _PAGE_PKEY_MASK) >> _PAGE_BIT_PKEY_BIT0;
1598#else
1599 return 0;
1600#endif
1601}
1602
1603static inline bool __pkru_allows_pkey(u16 pkey, bool write)
1604{
1605 u32 pkru = read_pkru();
1606
1607 if (!__pkru_allows_read(pkru, pkey))
1608 return false;
1609 if (write && !__pkru_allows_write(pkru, pkey))
1610 return false;
1611
1612 return true;
1613}
1614
1615/*
1616 * 'pteval' can come from a PTE, PMD or PUD. We only check
1617 * _PAGE_PRESENT, _PAGE_USER, and _PAGE_RW in here which are the
1618 * same value on all 3 types.
1619 */
1620static inline bool __pte_access_permitted(unsigned long pteval, bool write)
1621{
1622 unsigned long need_pte_bits = _PAGE_PRESENT|_PAGE_USER;
1623
1624 /*
1625 * Write=0,Dirty=1 PTEs are shadow stack, which the kernel
1626 * shouldn't generally allow access to, but since they
1627 * are already Write=0, the below logic covers both cases.
1628 */
1629 if (write)
1630 need_pte_bits |= _PAGE_RW;
1631
1632 if ((pteval & need_pte_bits) != need_pte_bits)
1633 return 0;
1634
1635 return __pkru_allows_pkey(pkey: pte_flags_pkey(pte_flags: pteval), write);
1636}
1637
1638#define pte_access_permitted pte_access_permitted
1639static inline bool pte_access_permitted(pte_t pte, bool write)
1640{
1641 return __pte_access_permitted(pteval: pte_val(pte), write);
1642}
1643
1644#define pmd_access_permitted pmd_access_permitted
1645static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1646{
1647 return __pte_access_permitted(pteval: pmd_val(pmd), write);
1648}
1649
1650#define pud_access_permitted pud_access_permitted
1651static inline bool pud_access_permitted(pud_t pud, bool write)
1652{
1653 return __pte_access_permitted(pteval: pud_val(pud), write);
1654}
1655
1656#define __HAVE_ARCH_PFN_MODIFY_ALLOWED 1
1657extern bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot);
1658
1659static inline bool arch_has_pfn_modify_check(void)
1660{
1661 return boot_cpu_has_bug(X86_BUG_L1TF);
1662}
1663
1664#define arch_check_zapped_pte arch_check_zapped_pte
1665void arch_check_zapped_pte(struct vm_area_struct *vma, pte_t pte);
1666
1667#define arch_check_zapped_pmd arch_check_zapped_pmd
1668void arch_check_zapped_pmd(struct vm_area_struct *vma, pmd_t pmd);
1669
1670#define arch_check_zapped_pud arch_check_zapped_pud
1671void arch_check_zapped_pud(struct vm_area_struct *vma, pud_t pud);
1672
1673#ifdef CONFIG_XEN_PV
1674#define arch_has_hw_nonleaf_pmd_young arch_has_hw_nonleaf_pmd_young
1675static inline bool arch_has_hw_nonleaf_pmd_young(void)
1676{
1677 return !cpu_feature_enabled(X86_FEATURE_XENPV);
1678}
1679#endif
1680
1681#ifdef CONFIG_PAGE_TABLE_CHECK
1682static inline bool pte_user_accessible_page(pte_t pte)
1683{
1684 return (pte_val(pte) & _PAGE_PRESENT) && (pte_val(pte) & _PAGE_USER);
1685}
1686
1687static inline bool pmd_user_accessible_page(pmd_t pmd)
1688{
1689 return pmd_leaf(pte: pmd) && (pmd_val(pmd) & _PAGE_PRESENT) && (pmd_val(pmd) & _PAGE_USER);
1690}
1691
1692static inline bool pud_user_accessible_page(pud_t pud)
1693{
1694 return pud_leaf(pud) && (pud_val(pud) & _PAGE_PRESENT) && (pud_val(pud) & _PAGE_USER);
1695}
1696#endif
1697
1698#ifdef CONFIG_X86_SGX
1699int arch_memory_failure(unsigned long pfn, int flags);
1700#define arch_memory_failure arch_memory_failure
1701
1702bool arch_is_platform_page(u64 paddr);
1703#define arch_is_platform_page arch_is_platform_page
1704#endif
1705
1706/*
1707 * Use set_p*_safe(), and elide TLB flushing, when confident that *no*
1708 * TLB flush will be required as a result of the "set". For example, use
1709 * in scenarios where it is known ahead of time that the routine is
1710 * setting non-present entries, or re-setting an existing entry to the
1711 * same value. Otherwise, use the typical "set" helpers and flush the
1712 * TLB.
1713 */
1714#define set_pte_safe(ptep, pte) \
1715({ \
1716 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \
1717 set_pte(ptep, pte); \
1718})
1719
1720#define set_pmd_safe(pmdp, pmd) \
1721({ \
1722 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \
1723 set_pmd(pmdp, pmd); \
1724})
1725
1726#define set_pud_safe(pudp, pud) \
1727({ \
1728 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \
1729 set_pud(pudp, pud); \
1730})
1731
1732#define set_p4d_safe(p4dp, p4d) \
1733({ \
1734 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \
1735 set_p4d(p4dp, p4d); \
1736})
1737
1738#define set_pgd_safe(pgdp, pgd) \
1739({ \
1740 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \
1741 set_pgd(pgdp, pgd); \
1742})
1743#endif /* __ASSEMBLER__ */
1744
1745#endif /* _ASM_X86_PGTABLE_H */
1746

source code of linux/arch/x86/include/asm/pgtable.h