Luca Fehlings fehlings · he/him
  • Groningen, The Netherlands
  • https://fehlings.github.io
  • Engineer working on memory devices & circuits. Currently PhD student @ University of Groningen

  • Joined on 2023-04-01
Boilerplate code to create matplotlib-based publication-ready plots
Updated 2026-02-15 10:29:56 +01:00
VACASK is a Verilog-A Circuit Analysis Kernel - an analog circuit simulator with a device library built from Verilog-A modules
Updated 2026-01-28 14:20:56 +01:00