Luca Fehlings fehlings · he/him

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• Groningen, The Netherlands
• https://fehlings.github.io

• Engineer working on memory devices & circuits. Currently PhD student @ University of Groningen

• Joined on 2023-04-01

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boilerplot

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Boilerplate code to create matplotlib-based publication-ready plots

data-science matplotlib paper visualization

Updated 2026-02-15 10:29:56 +01:00

VACASK

C++ 0 0

VACASK is a Verilog-A Circuit Analysis Kernel - an analog circuit simulator with a device library built from Verilog-A modules

Updated 2026-01-28 14:20:56 +01:00